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參數(shù)資料
| 型號(hào)： | SP9500AS |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 7.5 us SETTLING TIME, 12-BIT DAC, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 157K |
| 代理商： | SP9500AS |
SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
5
VOUT
VREF
DAC
12
1
SHIFT
REGISTER
DIN
–
+
–
+
DIN
VREF
VOUT
VDAC
VOUT
VDAC
DIN
WHERE…
=
4096
x (VREF - AGND) + AGND
()
LATCH
12
AGND
DAC
REGISTER
DAC
REGISTER
Figure 1. Detailed Block Diagram
USING THE SP9500
External Reference
The R-2R DAC input resistance is code depen-
dent and is minimum (11k
) at code 1365 and
2731. And, it is nearly infinite at code 0. Be-
cause of the code-dependent nature of the refer-
ence inputs, a high quality, low output imped-
ance amplifier should be used to drive the V
REF
and AGND inputs.
Serial Clock and Update Rate
The SP9500 maximum serial clock rate (SCLK)
is given by 1/(t
CH+tCL) which is approximately
12.5 MHz. The digital word update rate is lim-
ited by the chip select period, which is 12 X
Figure 2. Transfer Function
SCLK periods plus the CS high pulse width t
CSW.
This is equal to a 1
s or 1 MHz update rate.
However, the DAC settling time to 12–Bits is 7.5
s, which for full scale output transitions would
limit the update rate to 125 kHz.
Logic Interface
The SP9500 is designed to be compatible with
TTL and CMOS logic levels. However, driving
the digital inputs with TTL level signals will
increase the power consumption of the part by
300
A. In order to achieve the lowest power
consumption use rail-to-rail CMOS levels to
drive the digital inputs.
+0.5 lsb
DNLE
-0.5 lsb
+0.5 lsb
INLE
-0.5 lsb
0
CODE
4095
DNLE, INLE Plots
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SP9500BN | SERIAL INPUT LOADING, 7.5 us SETTLING TIME, 12-BIT DAC, PDIP8 |
| SP9500BS | SERIAL INPUT LOADING, 7.5 us SETTLING TIME, 12-BIT DAC, PDSO8 |
| SP9500AN | SERIAL INPUT LOADING, 7.5 us SETTLING TIME, 12-BIT DAC, PDIP8 |
| SP9501AN | SERIAL INPUT LOADING, 4 us SETTLING TIME, 12-BIT DAC, PDIP8 |
| SP9501BS | SERIAL INPUT LOADING, 4 us SETTLING TIME, 12-BIT DAC, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP9500BN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit, Voltage Output D/A Converter |
| SP9500BS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit, Voltage Output D/A Converter |
| SP9500JN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit, Voltage Output D/A Converter |
| SP9500JS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit, Voltage Output D/A Converter |
| SP9500KN | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit, Voltage Output D/A Converter |
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