參數(shù)資料
型號: SN74LVTH16652MEAX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 總線收發(fā)器
英文描述: LVT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
封裝: 0.300 INCH, MO-118, SSOP-56
文件頁數(shù): 4/9頁
文件大小: 87K
代理商: SN74LVTH16652MEAX
www.fairchildsemi.com
4
74L
VTH16652
Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both.
The select (SABn, SBAn) controls can multiplex stored and
real-time.
The examples below demonstrate the four fundamental
bus-management functions that can be performed with the
LVTH16652.
Data on the A or B data bus, or both can be stored in the
internal D flip-flop by LOW-to-HIGH transitions at the
appropriate Clock Inputs (CPABn, CPBAn) regardless of
the Select or Output Enable Inputs. When SAB and SBA
are in the real time transfer mode, it is also possible to
store data without using the internal D flip-flops by simulta-
neously enabling OEABn and OEBAn. In this configuration
each Output reinforces its Input. Thus when all other data
sources to the two sets of bus lines are in a HIGH imped-
ance state, each set of bus lines will remain at its last state.
Real-Time Transfer
Bus B to Bus A
Storage
Real-Time Transfer
Bus A to Bus B
Transfer Storage
Data to A or B
OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1
LL
X
L
OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1
XH
XX
X
LX
X
XX
LH
XX
OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1
HH
X
L
X
OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1
HL
H or L
H
相關PDF資料
PDF描述
SN74LVTH16652MEA LVT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
SN74LVTH16835DGG LVT SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56
SN74LVTH240ADW LVT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20
SN74LVTH240ADBR LVT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20
SN74LVTH573DGVR LVT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20
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