參數(shù)資料
型號: SN74LS273
廠商: ON SEMICONDUCTOR
英文描述: LOW POWER SCHOTTKY
中文描述: 低功耗肖特基
文件頁數(shù): 4/8頁
文件大?。?/td> 117K
代理商: SN74LS273
SN74LS273
http://onsemi.com
4
1.3 V
*The shaded areas indicate when the input is permitted to
*
change for predictable output performance.
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
CP
D
Q
n
t
s
(H)
t
h
(H)
t
s
(L)
t
h
(L)
1/f max
t
PLH
t
PLH
t
PHL
t
PHL
MR
CP
Q
n
Q
n
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
t
rec
t
PHL
t
PLH
t
W
1.3 V
1.3 V
1.3 V
*
t
W
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
AC WAVEFORMS
DEFINITION OF TERMS
SETUP TIME (t
s
) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW-to-HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (t
h
) — is defined as the minimum time
following the clock transition from LOW-to-HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW-to-HIGH and still be recognized.
RECOVERY TIME (t
rec
) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH data to the Q outputs.
相關PDF資料
PDF描述
SN74LS273W OCTAL D-TYPE FLIP-FLOP WITH CLEAR
SN74LS273DW LOW POWER SCHOTTKY
SN74LS273N LOW POWER SCHOTTKY
SN74LS273DW OCTAL D FLIP-FLOP WITH CLEAR
SN74LS273N OCTAL D FLIP-FLOP WITH CLEAR
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