參數(shù)資料
型號: SN74LS253
廠商: ON SEMICONDUCTOR
英文描述: LOW POWER SCHOTTKY
中文描述: 低功耗肖特基
文件頁數(shù): 3/8頁
文件大?。?/td> 108K
代理商: SN74LS253
SN74LS253
http://onsemi.com
3
LOGIC DIAGRAM
E
0b
I
3b
I
2b
I
1b
I
0b
S
0
S
1
I
3a
I
2a
I
1a
I
0a
E
0a
Z
b
Z
a
14
1
2
6
7
3
4
5
9
11
13
10
12
15
V
CC
= PIN 16
GND = PIN 8
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The LS253 contains two identical 4-Input Multiplexers
with 3-state outputs. They select two bits from four sources
selected by common select inputs (S
0
, S
1
). The 4-input
multiplexers have individual Output Enable (E
0a
, E
0b
)
inputs which when HIGH, forces the outputs to a high
impedance (high Z) state.
The LS253 is the logic implementation of a 2-pole,
4-position switch, where the position of the switch is
determined by the logic levels supplied to the two select
inputs. The logic equations for the outputs are shown below:
If the outputs of 3-state devices are tied together, all but
one device must be in the high impedance state to avoid high
currents that would exceed the maximum ratings. Designers
should ensure that Output Enable signals to 3-state devices
whose outputs are tied together are designed so that there is
no overlap.
Z
a
= E
0a
(I
0a
S
1
S
0
+ I
1a
S
1
S
0
I
2a
S
1
S
0
+ I
3a
S
1
S
0
)
Z
b
= E
0b
(I
0b
S
1
S
0
+ I
1b
S
1
S
0
I
2b
S
1
S
0
+ I
3b
S
1
S
0
)
TRUTH TABLE
SELECT
INPUTS
DATA INPUTS
OUTPUT
ENABLE
OUTPUT
S
0
S
1
I
0
I
1
I
2
I
3
E
0
Z
X
L
L
H
H
L
L
H
H
X
L
L
L
L
H
H
H
H
X
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
H
L
L
L
L
L
L
L
L
(Z)
L
H
L
H
L
H
L
H
H = HIGH Level
L = LOW Level
X = Irrelevant
(Z) = High Impedance (off)
Address inputs S
0
and S
1
are common to both sections.
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