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| 型號： | SN74GTLP21395PW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY |
| 中文描述： | 兩個1位LVTTL至GTLP可調EDGE的速率總線收發(fā)器與劈開LVTTL港口，反饋路徑，和可選的極性 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大小： | 439K |
| 代理商： | SN74GTLP21395PW |
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C
–
JUNE 2001
–
REVISED NOVEMBER 2001
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
skew characteristics over recommended ranges of supply voltage and operating free-air
temperature, V
REF
= 1 V, standard lumped loads (C
L
= 30 pF for B port and C
L
= 50 pF for Y port)
(unless otherwise noted)(see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE
MIN
MAX
UNIT
tsk(LH)
§
tsk(HL)
§
tsk(LH)
§
tsk(HL)
§
tsk(LH)
§
tsk(HL)
§
A
B
Slow
0.3
ns
0.4
A
B
Fast
0.3
ns
0.3
B
Y
0.4
ns
0.2
A
B
Slow
1.8
tsk(t)
§
( )
Fast
1.5
ns
B
Y
1
tsk(prLH)
tsk(prHL)
tsk(prLH)
tsk(prHL)
tsk(prLH)
tsk(prHL)
A
B
Slow
0.7
ns
2
A
B
Fast
0.5
ns
1.7
B
Y
1.2
ns
1.6
Actual skew values between GTLP outputs could vary on the backplane due to the loading and impedance seen by the device.
Slow (ERC = L) and Fast (ERC = H)
§
tsk(LH)/tsk(HL) and tsk(t)
–
Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all
outputs with the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs
switching in the same direction either high to low [tsk(HL)] or low to high [tsk(LH)] or in opposite directions, both low to high and high to low [tsk(t)].
tsk(prLH)/tsk(prHL)
–
The magnitude of the difference in propagation delay times between corresponding terminals of two logic devices when both
logic devices operate with the same supply voltages and at the same temperature, and have identical package types, identical specified loads,
and identical logic functions. Furthermore, these values are provided by SPICE simulations.
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相關代理商/技術參數(shù) |
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| SN74GTLP21395PWE4 | 功能描述:總線收發(fā)器 Quad Bus Buff Gate W/3-St Otpt RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74GTLP21395PWG4 | 功能描述:特定功能邏輯 Two 1B LVTTL GTLP Adj Edg RateBus Xcvr RoHS:否 制造商:Texas Instruments 產品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74GTLP21395PWR | 功能描述:轉換 - 電壓電平 Dual 1bit LVTTL-GTLP RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP22033DGGR | 功能描述:轉換 - 電壓電平 8bit LVTTL-GTLP RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP22033DGVR | 功能描述:特定功能邏輯 8bit LVTTL-GTLP RoHS:否 制造商:Texas Instruments 產品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
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