參數(shù)資料
型號(hào): SN74GTLP21395DWR
廠商: Texas Instruments, Inc.
英文描述: TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
中文描述: 兩個(gè)1位LVTTL至GTLP可調(diào)EDGE的速率總線收發(fā)器與劈開(kāi)LVTTL港口,反饋路徑,和可選的極性
文件頁(yè)數(shù): 14/21頁(yè)
文件大?。?/td> 439K
代理商: SN74GTLP21395DWR
SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C
JUNE 2001
REVISED NOVEMBER 2001
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
SN74GTLP21395 interface with the TSB14AA1 1394 backplane PHY
1A, 1B, and 1Y are used for the PHY data signals.
2A, 2B, and 2Y are used for the PHY strobe signals.
PHY N_OEB_D or OCDOE connects to 1OEAB and 2OEAB, which control the PHY transmit signals.
1OEBY and 2OEBY are connected to GND because the transceiver must always be able to receive signals
from the backplane and relay them to the PHY.
1T/C and 2T/C are connected to GND for inverted signals.
V
CC
is nominal 3.3 V.
BIAS V
CC
is connected to nominal 3.3 V to support live insertion.
V
REF
is normally 2/3 of V
TT
.
ERC is normally connected to V
CC
for slow edge-rate operation because frequencies of only 50 MHz (S100)
and 25 MHz (S50) are required.
logical representation
1394
Link-
Layer
Controller
Host
Interface
D0
D1
CTL0
CTL1
LREQ
SCLK
1394
Backplane
Physical-
Layer
Controller
TSB14AA1
3.3-V VCC
BPdata
BPstrb
Tdata
Rdata
Rstrb
Tstrb
OCDOE
1A
1Y
2A
2Y
GND
2OEBY
2OEAB
1B
2B
SN74GTLP21395
2
2
1 k
TDOE
VCC
GND
1OEBY
GND
2T/C
1T/C
GND
1OEAB
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SN74GTLP21395PWG4 功能描述:特定功能邏輯 Two 1B LVTTL GTLP Adj Edg RateBus Xcvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube
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