參數(shù)資料
型號(hào): SN74CBTLV16800DGV
廠商: Texas Instruments, Inc.
英文描述: LOW-VOLTAGE 20-BIT FET BUS SWITCH WITH PRECHARGED OUTPUTS
中文描述: 低電壓20位FET總線開關(guān)與預(yù)充電輸出
文件頁(yè)數(shù): 4/6頁(yè)
文件大?。?/td> 84K
代理商: SN74CBTLV16800DGV
SN74CBTLV16800
LOW-VOLTAGE 20-BIT FET BUS SWITCH
WITH PRECHARGED OUTPUTS
SCDS045F – DECEMBER 1997 – REVISED MAY 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
PARAMETER
TEST
CONDITIONS
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.5 V
±
0.2 V
VCC = 3.3 V
±
0.3 V
UNIT
MIN
MAX
MIN
MAX
tpd
tPZH
tPZL
tPHZ
tPLZ
A or B
B or A
0.35
0.25
ns
BIASV = GND
OE
A or B
2.9
7.7
2.2
5.5
ns
BIASV = 3 V
2.8
6.4
2.1
5.3
BIASV = GND
OE
A or B
1.4
6.8
2.6
7.6
ns
BIASV = 3 V
1.3
4.2
1.5
5.1
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.5 V
±
0.2 V
VCC/2
VCC/2
VCC/2
VCC/2
VOH
VOL
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
×
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2
×
VCC
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2 ns, tf
2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLH and tPHL are the same as tpd.
tPHL
VCC/2
VCC/2
VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2
VCC/2
tPLH
2
×
VCC
VCC
Figure 1. Load Circuit and Voltage Waveforms
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