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參數(shù)資料
| 型號： | SN74ACT7802PN |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1024 】 18 STROBED FIRST-IN, FIRST-OUT MEMORY |
| 中文描述： | 1024】18選通先入先出存儲器 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 156K |
| 代理商： | SN74ACT7802PN |
SN74ACT7802
1024
×
18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS187D – AUGUST 1990 – REVISED APRIL 1998
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
22 23
V
CC
V
CC
NC
Q3
Q2
GND
Q1
Q0
V
CC
HF
FULL
GND
GND
AF/AE
V
CC
NC
NC
LDCK
GND
NC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC
GND
GND
Q16
Q17
V
CC
EMPTY
GND
V
CC
RESET
OE
NC
NC
UNCK
GND
D17
D16
D15
NC
NC
25 26 27 28
PN PACKAGE
(TOP VIEW)
Q
79 78 77 76 75
80
74
Q
Q
G
G
Q
Q
Q
D
D
D
D
D
D
D
D
72 71 70
73
29 30 31 32 33
69 68
21
N
Q
67 66 65 64
34 35 36 37
D
D
D
D
Q
Q
Q
Q
D
D
38 39 40
G
G
63 62 61
V
C
G
Q
C
V
D
D
N
G
V
C
NC – No internal connection
V
C
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT7802 is a 1024-word by 18-bit FIFO for high-speed applications. It processes data
in a bit-parallel format at rates up to 40 MHz and access times of 30 ns.
Data is written into the FIFO memory on a low-to-high transition on the load-clock (LDCK) input and is read out
on a low-to-high transition on the unload-clock (UNCK) input. The memory is full when the number of words
clocked in exceeds by 1024 the number of words clocked out. When the memory is full, LDCK has no effect on
the data in the memory; when the memory is empty, UNCK has no effect.
A low level on the reset (RESET) input resets the FIFO internal clock stack pointers and sets full (FULL) high,
almost full/almost empty (AF/AE) high, half full (HF) low, and empty (EMPTY) low. The Q outputs are not reset
to any specific logic level. The FIFO must be reset upon power up. The Q outputs are noninverting and are in
the high-impedance state when the output-enable (OE) input is low.
When writing to the FIFO after a reset pulse or when the FIFO is empty, the first active transition on LDCK drives
EMPTY high and causes the first word written to the FIFO to appear on the Q outputs. An active transition on
UNCK is not required to read the first word written to the FIFO. Each subsequent read from the FIFO requires
an active transition on UNCK.
The SN74ACT7802 can be cascaded in the word-width direction but not in the word-depth direction.
The SN74ACT7802 is characterized for operation from 0
°
C to 70
°
C.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74ACT7803-15DL | 功能描述:先進(jìn)先出 512 x 18 synchronous 先進(jìn)先出 memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ACT7803-15DLR | 功能描述:先進(jìn)先出 512 x 18 synchronous 先進(jìn)先出 memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ACT7803-20DL | 功能描述:先進(jìn)先出 512 x 18 synchronous 先進(jìn)先出 memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ACT7803-20DLR | 功能描述:先進(jìn)先出 512 x 18 synchronous 先進(jìn)先出 memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ACT7803-25DL | 功能描述:先進(jìn)先出 512 x 18 synchronous 先進(jìn)先出 memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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