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參數(shù)資料
| 型號： | SN74ACT3641PQ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Low-Voltage Quad 2-Input OR Gate with 5V-Tolerant Inputs, Pb-free; Package: SOEIAJ-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2000 |
| 中文描述： | 1024】36時鐘先入先出存儲器 |
| 文件頁數(shù)： | 22/26頁 |
| 文件大?。?/td> | 379K |
| 代理商： | SN74ACT3641PQ |
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SN74ACT3641
1024
×
36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 16)
’ACT3641-15
MIN
’ACT3641-20
MIN
’ACT3641-30
MIN
UNIT
MAX
MAX
MAX
fclock
tc
tw(CH)
tw(CL)
tsu(D)
tsu(EN1)
Clock frequency, CLKA or CLKB
66.7
50
33.4
MHz
Clock cycle time, CLKA or CLKB
15
20
30
ns
Pulse duration, CLKA and CLKB high
6
8
12
ns
Pulse duration, CLKA and CLKB low
Setup time, A0–A35 before CLKA
↑
and B0–B35 before CLKB
↑
Setup time, ENA to CLKA
↑
; ENB to CLKB
↑
Setup time, CSA, W/RA, and MBA to CLKA
↑
;
CSB, W/RB, and MBB to CLKB
↑
Setup time, RTM and RFM to CLKB
↑
Setup time, RST low before CLKA
↑
or CLKB
↑
Setup time, FS0 and FS1 before RST high
Setup time, FS0/SD before CLKA
↑
Setup time, FS1/SEN before CLKA
↑
Hold time, A0–A35 after CLKA
↑
and B0–B35 after CLKB
↑
Hold time, ENA after CLKA
↑
; ENB after CLKB
↑
Hold time, CSA, W/RA, and MBA after CLKA
↑
;
CSB, W/RB, and MBB after CLKB
↑
Hold time, RTM and RFM after CLKB
↑
Hold time, RST low after CLKA
↑
or CLKB
↑
Hold time, FS0 and FS1 after RST high
6
8
12
ns
5
6
7
ns
5
6
7
ns
tsu(EN2)
7
7.5
8
ns
tsu(RM)
tsu(RS)
tsu(FS)
tsu(SD)
tsu(SEN)
th(D)
tn(EN1)
6
6.5
7
ns
5
6
7
ns
9
10
11
ns
5
6
7
ns
5
6
7
ns
0
0
0
ns
0
0
0
ns
tn(EN2)
0
0
0
ns
tn(RM)
th(RS)
th(FS)
th(SP)
th(SD)
th(SEN)
tsk(1)§
tsk(2)§
Requirement to count the clock edge as one of at least four needed to reset a FIFO
Applies only when serial load method is used to program flag-offset registers
§Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and
CLKB cycle.
0
0
0
ns
5
6
7
ns
0
0
0
ns
Hold time, FS1/SEN high after RST high
Hold time, FS0/SD after CLKA
↑
Hold time, FS1/SEN after CLKA
↑
Skew time between CLKA
↑
and CLKB
↑
for OR and IR
Skew time between CLKA
↑
and CLKB
↑
for AE and AF
0
0
0
ns
0
0
0
ns
0
0
0
ns
9
11
13
ns
12
16
20
ns
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| SN74ACT3651-15PCB | 功能描述:先進(jìn)先出 2048 x 36 synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ACT3651-15PQ | 功能描述:先進(jìn)先出 2048 x 36 synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ACT3651-20PBC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN74ACT3651-20PCB | 功能描述:先進(jìn)先出 2048 x 36 synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ACT3651-20PQ | 功能描述:先進(jìn)先出 2048 x 36 synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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