參數(shù)資料
型號: SN74ACT3641PQ
廠商: Texas Instruments, Inc.
英文描述: Low-Voltage Quad 2-Input OR Gate with 5V-Tolerant Inputs, Pb-free; Package: SOEIAJ-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2000
中文描述: 1024】36時鐘先入先出存儲器
文件頁數(shù): 16/26頁
文件大小: 379K
代理商: SN74ACT3641PQ
SN74ACT3641
1024
×
36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
(X + 1) Words in FIFO
ììììì
ììììì
CLKA
AE
ENB
ENA
tsu(EN1)
tsk(2)
tpd(C-AE)
X Words in FIFO
1
CLKB
2
tpd(C-AE)
th(EN1)
ììììì
ììììì
tsk(2) is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition high in the next CLKB cycle. If the time
between the rising CLKA edge and rising CLKB edge is less than tsk(2), AE can transition high one CLKB cycle later than shown.
NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L)
Figure 8. Timing for AE When FIFO Is Almost Empty
(1024 – Y) Words in FIFO
tpd(C-AF)
ììììì
ììììì
CLKA
AF
ENB
ENA
tsu(EN1)
th(EN1)
[1024 – (Y + 1)] Words in FIFO
th(EN1)
tsk(2)
1
2
ììììì
ììììì
CLKB
tsk(2) is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition high in the next CLKA cycle. If the time
between the rising CLKB edge and rising CLKA edge is less than tsk(2), AF can transition high one CLKA cycle later than shown.
NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L)
Figure 9. Timing for AF When FIFO Is Almost Full
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
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