參數(shù)資料
型號(hào): SN74ACT3638PQ
廠商: Texas Instruments, Inc.
英文描述: Low-Voltage Quad 2-Input OR Gate with 5V-Tolerant Inputs; Package: TSSOP-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2500
中文描述: 512】32】2時(shí)鐘雙向先入先出存儲(chǔ)器
文件頁(yè)數(shù): 20/30頁(yè)
文件大?。?/td> 461K
代理商: SN74ACT3638PQ
SN74ACT3638
512
×
32
×
2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
tpd(C-AF)
tpd(C-AF)
ììììì
ììììì
CLKA
AFA
ENB
ENA
[512 – (Y1 + 1)] Words in FIFO1
tsk2
1
2
ììììì
ììììì
CLKB
(512 – Y1) Words in FIFO1
tsk2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition high in the next CLKA cycle. If the time
between the rising CLKA edge and rising CLKB edge is less than tsk2, then AFA may transition high one CLKB cycle later than shown.
NOTE A: FIFO1 write (CSA = L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = H, MBB = L). Data in the FIFO1 output register has been
read from the FIFO.
Figure 15. Timing for AFA When FIFO1 Is Almost Full
tpd(C-AF)
tpd(C-AF)
tsu(EN)
ììììì
CLKB
AFB
ENA
ENB
tsu(EN)
th(EN)
[512 – (Y2 + 1)] Words in FIFO2
th(EN)
tsk2
1
2
ììììì
CLKA
(512 – Y2) Words in FIFO2
tsk2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition high in the next CLKB cycle. If the time
between the rising CLKB edge and rising CLKA edge is less than tsk2, then AFB may transition high one CLKA cycle later than shown.
NOTE A: FIFO2 write (CSB = L, W/RB = L, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L). Data in the FIFO2 output register has been
read from the FIFO.
Figure 16. Timing for AFB When FIFO2 Is Almost Full
相關(guān)PDF資料
PDF描述
SN74ACT3641PCB Low-Voltage Quad 2-Input OR Gate with 5V-Tolerant Inputs; Package: SOEIAJ-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2000
SN74ACT3641PQ Low-Voltage Quad 2-Input OR Gate with 5V-Tolerant Inputs, Pb-free; Package: SOEIAJ-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2000
SN74ACT3651PCB Low-Voltage CMOS Octal Transparent Latch; Package: TSSOP 20 LEAD; No of Pins: 20; Container: Rail; Qty per Container: 75
SN74ACT3651PQ Low-Voltage CMOS Octal Transparent Latch; Package: TSSOP 20 LEAD; No of Pins: 20; Container: Tape and Reel; Qty per Container: 2500
SN74ACT373DB OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
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SN74ACT3641-15PQ 功能描述:先進(jìn)先出 1024 x 36 synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
SN74ACT3641-20PCB 功能描述:先進(jìn)先出 1024 x 36 synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
SN74ACT3641-20PQ 功能描述:先進(jìn)先出 1024 x 36 synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
SN74ACT3641-30PCB 功能描述:先進(jìn)先出 1024 x 36 synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: