參數(shù)資料
型號(hào): SN74ACT3638PCB
廠商: Texas Instruments, Inc.
英文描述: 512 】 32 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
中文描述: 512】32】2時(shí)鐘雙向先入先出存儲(chǔ)器
文件頁數(shù): 19/30頁
文件大小: 461K
代理商: SN74ACT3638PCB
SN74ACT3638
512
×
32
×
2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
tpd(W-R)
W/RA
RDYA
Inverse of ORA
Inverse of IRA
tpd(W-R)
Figure 11. W/RA to RDYA Timing
ìììììììì
tpd(W-R)
W/RB
RDYB
Inverse of ORB
Inverse of IRB
tpd(W-R)
Figure 12. W/RB to RDYB Timing
tpd(C-AE)
tsu(EN)
CLKA
AEB
ENB
ENA
th(EN)
tsu(EN)
tsk2
X1 Words in FIFO1
1
CLKB
2
tpd(C-AE)
ììììì
(X1 + 1) Words in FIFO1
ììììì
ììììì
tsk2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition high in the next CLKB cycle. If the time
between the rising CLKA edge and rising CLKB edge is less than tsk2, then AEB may transition high one CLKB cycle later than shown.
NOTE A: FIFO1 write (CSA = L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = H, MBB = L). Data in the FIFO1 output register has been
read from the FIFO.
Figure 13. Timing for AEB When FIFO1 Is Almost Empty
tsu(EN)
CLKB
AEA
ENA
ENB
th(EN)
tsu(EN)
tpd(C-AE)
X2 Words in FIFO2
1
CLKA
2
tpd(C-AE)
th(EN)
ììììì
ììììì
(X2 + 1) Words in FIFO2
ììììì
tsk2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition high in the next CLKA cycle. If the time
between the rising CLKB edge and rising CLKA edge is less than tsk2, then AEA may transition high one CLKA cycle later than shown.
NOTE A: FIFO2 write (CSB = L, W/RB = L, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L). Data in the FIFO2 output register has been
read from the FIFO.
Figure 14. Timing for AEA When FIFO2 Is Almost Empty
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