參數(shù)資料
型號: SN74ABT7820PH
廠商: Texas Instruments, Inc.
英文描述: 512 】 18 】 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
中文描述: 512】18】2選通雙向先入先出存儲器
文件頁數(shù): 2/15頁
文件大?。?/td> 196K
代理商: SN74ABT7820PH
SN74ABT7820
512
×
18
×
2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS206D – AUGUST 1991 – REVISED APRIL 1998
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
A
G
V
C
A
B
A
A
G
A
A
A
B
B
G
B
B
B
B
G
P
S
G
U
E
E
U
S
G
P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25
60
59
58
57
56
55
54
53
52
51
50
48
47
46
49
45
44
43
42
41
40
26 27 28 29 30 31 32 33 34 35 36 37 38 39
80 79 78 77 76 75 74 73
71 70 69 68 67 66 65 64 63 62 61
72
V
C
PN PACKAGE
(TOP VIEW)
R
G
L
L
G
R
AF/AEA
HFA
FULLA
GND
A0
A1
V
CC
A2
A3
GND
A4
A5
GND
A6
A7
GND
A8
A9
V
CC
A10
AF/AEB
HFB
FULLB
GND
B0
B1
V
CC
B2
B3
GND
B4
B5
GND
B6
B7
GND
B8
B9
V
CC
B10
C
C
C
C
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ABT7820 is arranged as two 512
×
18-bit FIFOs for high speed and fast access times. It
processes data at rates up to 67 MHz with access times of 12 ns in a bit-parallel format.
The SN74ABT7820 consists of bus-transceiver circuits, two 512
×
18 FIFOs, and control circuitry arranged for
multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable inputs
(GAB and GBA) control the transceiver functions. The SAB and SBA control inputs select whether real-time or
stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the eight
fundamental bus-management functions that can be performed with the SN74ABT7820.
The SN74ABT7820 is characterized for operation from 0
°
C to 70
°
C.
相關(guān)PDF資料
PDF描述
SN74ABT7820PN 512 】 18 】 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
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