參數(shù)資料
型號(hào)： SN74ABT7819A-12PH
廠商： Texas Instruments, Inc.
英文描述： 512 】 18 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
中文描述： 512】18】2時(shí)鐘雙向先入先出存儲(chǔ)器
文件頁(yè)數(shù)： 3/21頁(yè)
文件大?。?/td> 324K
代理商： SN74ABT7819A-12PH
SN74ABT7819A
512
×
18
×
2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756
–
MAY 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
The state of the B0
–
B17 outputs is controlled by the port-B chip select (CSB) and the port-B write/read select
(W/RB). When both CSB and W/RB are low, the outputs are active. The B0
–
B17 outputs are in the
high-impedance state when either CSB or W/RB is high. Data is written to FIFOB
–
A from port B on the
low-to-high transition of the port-B clock (CLKB) when CSB is low, W/RB is high, the port-B write enable (WENB)
is high, and the port-B input-ready (IRB) flag is high. Data is read from FIFOA
–
B to the B0
–
B17 outputs on the
low-to-high transition of CLKB when CSB is low, W/RB is low, the port-B read enable (RENB) is high, and the
port-B output-ready (ORB) flag is high.
The setup- and hold-time constraints for the chip selects (CSA, CSB) and write/read selects (W/RA, W/RB)
enable write and read operations on memory and are not related to the high-impedance control of the data
outputs. If a port read enable (RENA or RENB) and write enable (WENA or WENB) are set low during a clock
cycle, the chip select and write/read select can switch at any time during the cycle to change the state of the
data outputs.
The input-ready (IR) and output-ready (OR) flags of a FIFO are two-stage synchronized to the port clocks for
use as reliable control signals. CLKA synchronizes the status of the input-ready flag of FIFOA
–
B (IRA) and the
output-ready flag of FIFOB
–
A (ORA). CLKB synchronizes the status of the input-ready flag of FIFOB
–
A (IRB)
and the output-ready flag of FIFOA
–
B (ORB). When the IR flag of a port is low, the FIFO receiving input from
the port is full and writes are disabled to its array. When the OR flag of a port is low, the FIFO that outputs data
to the port is empty and reads from its memory are disabled. The first word loaded to an empty memory is sent
to the FIFO output register at the same time its OR flag is asserted (high). When the memory is read empty and
the OR flag is forced low, the last valid data remains on the FIFO outputs until the OR flag is asserted (high)
again. In this way, a high on the OR flag indicates new data is present on the FIFO outputs.
The SN74ABT7819A is characterized for operation from 0
°
C to 70
°
C.
Function Tables
PORT A
SELECT INPUTS
CSA
W/RA
A0 A17
A0–A17
PORT A OPERATION
PORT-A OPERATION
CLKA
WENA
RENA
X
↑
↑
H
X
X
X
High Z
None
L
H
H
X
High Z
Write A0
–
A17 to FIFOA
–
B
L
L
X
H
Active
Read FIFOB
–
A to A0
–
A17
PORT B
SELECT INPUTS
CSB
W/RB
B0 B17
B0–B17
PORT B OPERATION
PORT-B OPERATION
CLKB
WENB
RENB
X
↑
↑
H
X
X
X
High Z
None
L
H
H
X
High Z
Write B0
–
B17 to FIFOB
–
A
L
L
X
H
Active
Read FIFOA
–
B to B0
–
B17
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN74ABT7819A-12PN 功能描述:先進(jìn)先出 512x18x2 Clocked Bidir Mem RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
SN74ABT7819A-15PH 功能描述:特定功能邏輯 512x18x2 Clocked Bidir Mem RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube
SN74ABT7819A-15PN 功能描述:先進(jìn)先出 512x18x2 Clocked Bidir Mem RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
SN74ABT7819A-20PH 功能描述:特定功能邏輯 512x18x2 Clocked Bidir Mem RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube
SN74ABT7819A-20PN 功能描述:先進(jìn)先出 512x18x2 Clocked Bidir Mem RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
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