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參數(shù)資料
| 型號： | SN74ABT7819A-12PH |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 512 】 18 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY |
| 中文描述： | 512】18】2時鐘雙向先入先出存儲器 |
| 文件頁數(shù)： | 2/21頁 |
| 文件大小： | 324K |
| 代理商： | SN74ABT7819A-12PH |
SN74ABT7819A
512
×
18
×
2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756
–
MAY 2002
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
A
G
V
C
A
B
A
A
G
A
A
A
B
B
G
B
B
B
B
G
P
W
G
C
R
R
C
W
C
P
21 22 23 24 25
40
26 27 28 29 30 31 32 33 34 35 36 37 38 39
80 79 78 77 76 75 74 73
71 70 69 68 67 66 65 64 63 62 61
72
V
C
PN PACKAGE
(TOP VIEW)
R
C
W
W
G
R
AF/AEA
HFA
IRA
GND
A0
A1
V
CC
A2
A3
GND
A4
A5
GND
A6
A7
GND
A8
A9
V
CC
A10
AF/AEB
HFB
IRB
GND
B0
B1
V
CC
B2
B3
GND
B4
B5
GND
B6
B7
GND
B8
B9
V
CC
B10
C
V
C
V
O
O
1
2
3
4
5
6
7
8
9
10
11
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60
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description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ABT7819A is a high-speed, low-power, BiCMOS, bidirectional, clocked FIFO memory.
Two independent 512
×
18 dual-port SRAM FIFOs (FIFOA, FIFOB) on the chip buffer data in opposite directions.
Each FIFO has flags to indicate empty and full conditions, a half-full flag, and a programmable
almost-full/almost-empty flag.
The SN74ABT7819A is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.
The state of the A0
–
A17 outputs is controlled by the port-A chip select (CSA) and the port-A write/read select
(W/RA). When both CSA and W/RA are low, the outputs are active. The A0
–
A17 outputs are in the
high-impedance state when either CSA or W/RA is high. Data is written to FIFOA
–
B from port A on the
low-to-high transition of the port-A clock (CLKA) input when CSA is low, W/RA is high, the port-A write enable
(WENA) is high, and the port-A input-ready (IRA) flag is high. Data is read from FIFOB
–
A to the A0
–
A17 outputs
on the low-to-high transition of CLKA when CSA is low, W/RA is low, the port-A read enable (RENA) is high,
and the port-A output-ready (ORA) flag is high.
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| SN74ABT7820PH | 512 】 18 】 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74ABT7819A-12PN | 功能描述:先進先出 512x18x2 Clocked Bidir Mem RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ABT7819A-15PH | 功能描述:特定功能邏輯 512x18x2 Clocked Bidir Mem RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74ABT7819A-15PN | 功能描述:先進先出 512x18x2 Clocked Bidir Mem RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ABT7819A-20PH | 功能描述:特定功能邏輯 512x18x2 Clocked Bidir Mem RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74ABT7819A-20PN | 功能描述:先進先出 512x18x2 Clocked Bidir Mem RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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