參數(shù)資料
型號(hào)： SN65LVDT122DRG4
廠商： Texas Instruments, Inc.
英文描述： 1.5-Gbps 2 x 2 LVDS CROSSPOINT SWITCH
中文描述： 1.5 - Gbps的2 × 2 LVDS交叉點(diǎn)開(kāi)關(guān)
文件頁(yè)數(shù)： 4/18頁(yè)
文件大?。?/td> 544K
代理商： SN65LVDT122DRG4
www.ti.com
TIMING CHARACTERISTICS
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
SN65LVDS122
SN65LVDT122
SLLS525B–MAY 2002–REVISED JUNE 2004
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
ns
ns
ns
t
SET
t
HOLD
t
SWITCH
Input to select setup time
Input to select hold time
Select to switch output
0
0.5
1
2
2.6
PARAMETER
TEST CONDITIONS
MIN
400
400
NOM
(1)
650
650
MAX
900
900
280
280
50
100
2.2
17
65
50
UNIT
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
ps
t
PLH
t
PHL
t
r
t
f
t
sk(p)
t
sk(pp)
t
jit(per)
t
jit(cc)
t
jit(pp)
t
jit(det)
t
PHZ
t
PLZ
t
PZH
t
PZL
t
sk(o)
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time (20% - 80%)
Differential output signal fall time (20% - 80%)
Pulse skew (|t
PHL
- t
PLH
|)
(2)
Part-to-part skew
(3)
Period jitter, rms (1 standard deviation)
(4)
Cycle-to-cycle jitter (peak)
(4)
Peak-to-peak jitter
(4)
Deterministic jitter, peak-to-peak
(4)
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Output skew
(9)
See Figure 4
10
V
ID
= 0.2 V
750 MHz clock input
(5)
750 MHz clock input
(6)
1.5 Gbps 2
23
–1 PRBS input
(7)
1.5 Gbps 2
7
–1 PRBS input
(8)
See Figure 5
See Figure 5
See Figure 5
See Figure 5
1
10
33
17
6
6
4
4
15
8
8
6
6
40
(1)
(2)
(3)
All typical values are at 25
°
C and with a 3.3-V supply.
t
sk(p)
is the magnitude of the time difference between the t
and t
of any output of a single device.
t
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Jitter is specified by design and characterization. Stimulus jitter has been subtracted.
Input voltage = V
ID
= 200 mV, 50% duty cycle at 750 MHz, t
r
= t
f
= 50 ps (20% to 80%), measured over 1000 samples.
Input voltage = V
ID
= 200 mV, 50% duty cycle at 750 MHz, t
= t
f
= 50 ps (20% to 80%).
Input voltage = V
ID
= 200 mV, 2
23
–1 PRBS pattern at 1.5 Gbps, t
r
= t
f
= 50 ps (20% to 80%), measured over 200 k samples.
Input voltage = V
= 200 mV, 2
7
–1 PRBS pattern at 1.5 Gbps, t
= t
= 50 ps (20% to 80%).
Output skew is the magnitude of the time delay difference between the outputs of a single device with all inputs tied together.
(4)
(5)
(6)
(7)
(8)
(9)
4
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