參數(shù)資料
型號: SN54LS674W
廠商: Texas Instruments, Inc.
元件分類: 通用總線功能
英文描述: Quad 2-Input NAND Gate with Open Drain Outputs; Package: SOIC 14 LEAD; No of Pins: 14; Container: Rail; Qty per Container: 55
中文描述: 16位轉(zhuǎn)換寄存器
文件頁數(shù): 12/16頁
文件大?。?/td> 526K
代理商: SN54LS674W
MECHANICAL DATA
MLCC006B – OCTOBER 1996
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
(14,22)
0.458
0.858
(21,8)
1.063
(27,0)
A
NO. OF
TERMINALS
MIN
MAX
0.358
(9,09)
0.660
(16,76)
0.761
(19,32)
0.458
(11,63)
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
(18,78)
0.442
0.962
(24,43)
1.165
(29,59)
(23,83)
0.938
(28,99)
1.141
**
20
28
52
44
68
84
0.020 (0,51)
0.010 (0,25)
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
12
13
14
15
16
18
17
11
10
8
9
7
5
4
3
2
0.020 (0,51)
0.010 (0,25)
6
1
28
26
27
19
21
B SQ
A SQ
22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
相關PDF資料
PDF描述
SN54LS674JT 16-BIT SHIFT REGISTERS
SN54LS68 Quad 2-Input NAND Gate with Open Drain Outputs; Package: SOIC 14 LEAD; No of Pins: 14; Container: Rail; Qty per Container: 55
SN54LS78A 8-Bit Serial or Parallel-Input/Serial Output Shift Register; Package: SOEIAJ-16; No of Pins: 16; Container: Rail; Qty per Container: 50
SN54LS78AJ 8-Bit Serial or Parallel-Input/Serial Output Shift Register; Package: SOEIAJ-16; No of Pins: 16; Container: Tape and Reel; Qty per Container: 2000
SN54LS78AW 8-Bit Serial or Parallel-Input/Serial Output Shift Register; Package: SOEIAJ-16; No of Pins: 16; Container: Rail; Qty per Container: 50
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