參數(shù)資料
型號(hào)： SN54ABT8245JT
廠商： Texas Instruments, Inc.
英文描述： SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS
中文描述： 掃描測(cè)試設(shè)備與八進(jìn)制總線收發(fā)器
文件頁(yè)數(shù)： 12/25頁(yè)
文件大?。?/td> 364K
代理商： SN54ABT8245JT
SN54ABT8245, SN74ABT8245
SCAN TEST DEVICES
WITH OCTAL BUS TRANSCEIVERS
SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
control boundary to high impedance
This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in a modified test mode in which all device I/O pins are placed in the high-impedance state, the device
input pins remain operational, and the normal on-chip logic function is performed.
control boundary to 1/0
This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input
BSCs is applied to the inputs of the normal on-chip logic, while data in the output BSCs is applied to the device
output pins. The device operates in the test mode.
boundary run test
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during
Run-Test/Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),
PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up
(PSA/COUNT).
boundary read
The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This
instruction is useful for inspecting data after a PSA operation.
boundary self test
The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.
In this way, the contents of the shadow latches can be read out to verify the integrity of both shift-register and
shadow-latch elements of the BSR. The device operates in the normal mode.
boundary toggle outputs
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. Data in the shift-register elements of the selected output BSCs is toggled on each rising edge of
TCK in Run-Test/Idle, updated in the shadow latches, and applied to the associated device output pins on each
falling edge of TCK in Run-Test/Idle. Data in the selected input BSCs remains constant and is applied to the
inputs of the normal on-chip logic. Data appearing at the device input pins is not captured in the input BSCs.
The device operates in the test mode.
boundary-control register scan
The BCR is selected in the scan path. The value in the boundary-control register remains unchanged during
Capture-DR. This operation must be performed before a boundary run test operation to specify which test
operation is to be executed.
相關(guān)PDF資料
PDF描述
SN54ABT827FK 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN54ABT827JT 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74ABT827DB 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN54ABT833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SN54ABT833FK 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN54ABT827 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN54ABT827FK 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN54ABT827JT 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN54ABT833 制造商:TI 制造商全稱:Texas Instruments 功能描述:8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SN54ABT833FK 制造商:TI 制造商全稱:Texas Instruments 功能描述:8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
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