參數(shù)資料
型號: SMT4004F
廠商: Electronic Theatre Controls, Inc.
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Distributed Power Hot-Swap Controller
中文描述: 分布式電源熱插拔控制器
文件頁數(shù): 9/23頁
文件大?。?/td> 480K
代理商: SMT4004F
9
2049 2.2 9/13/00
SMT4004
SUMMIT MICROELECTRONICS, Inc.
Card- side Under-voltage Threshold Enable
and Over-voltage Offset
Registers
0C
,
0D
,
0E
and
0F
are identical These registers
will either enable or disable their associated power man-
agement functions and soft start capability. Their contents
also determine whether the under- or over-voltage capa-
bilities are enabled and the contents establish the over-
voltage offset value for the VO1, VO2, VO3 and VO4
inputs, respectively.
F
0
R
,
E
0
R
,
0
D
D
x
x
x
0
R
,
C
0
1
x
x
x
R
D
r
e
e
R
2
D
x
x
x
7
D
6
D
x
1
x
5
D
x
x
1
4
D
x
x
x
3
D
x
x
x
n
l
n
n
a
h
c
=
0
2
e
g
a
v
(
)
V
U
(
u
v
y
n
o
A
1
x
x
d
k
e
a
n
e
e
a
n
E
t
e
;
m
e
g
t
s
r
d
n
u
=
d
h
s
e
T
n
r
e
=
a
n
a
m
e
a
n
E
s
e
a
n
E
r
w
o
P
=
1
g
n
a
x
x
x
0
0
0
1
0
n
×
e
1
V
U
×
e
h
w
)
0
2049 Table04 1.0
Addressing and Slew Rate Control
Configuration Register
10
is used to configure the ad-
dressing protocol for the
TRAKKER
. Bit 7 determines
whether the device will respond with an acknowledge to
any bus request addressing its device type identifier, or
whether it will be selective and only respond if the A2, A1
and A0 bits match the biasing of the external pins. Bit 6
selects the device type identifier to be used for the memory
array.
0
1
1
R
D
r
e
e
R
2
D
7
D
6
D
5
D
4
D
3
D
0
D
n
o
A
n
o
0
x
x
s
u
b
d
e
s
a
y
o
s
s
s
d
d
d
e
d
n
s
s
n
o
p
s
e
R
m
e
M
m
e
M
n
o
a
n
g
t
h
S
R
T
t
h
S
R
T
e
G
)
o
0
0
1
0
5
2
0
0
5
0
0
1
)
0
1
5
2
0
5
0
1
o
p
s
e
e
d
a
R
1
x
x
x
0
1
s
1
1
e
s
s
e
d
a
e
d
e
d
s
e
e
u
p
p
b
l
y
c
e
y
c
e
o
0
1
1
1
0
0
r
r
y
y
l
e
V
m
0
0
3
r
d
n
u
v
o
R
E
K
K
A
R
T
x
0
0
x
e
0
1
d
n
a
y
p
u
s
y
a
e
h
#
l
#
Q
R
I
R
K
e
n
n
Q
n
w
R
w
o
d
I
R
K
d
1
0
d
n
a
s
e
p
u
s
o
1
1
#
Q
R
I
R
K
R
T
o
h
g
o
w
o
e
0
1
0
1
e
w
w
e
R
E
K
0
0
1
1
K
K
A
R
T
x
x
s
V
s
V
s
V
V
0
s
o
0
1
0
1
n
o
w
o
o
0
0
1
1
h
g
e
R
E
K
A
R
T
x
s
V
0
V
0
V
0
0
0
s
s
V
s
2049 Table05 1.0
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