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參數(shù)資料
| 型號： | SL2610LH1Q |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Wide Dynamic Range Image Reject MOPLL |
| 中文描述： | 寬動態(tài)范圍圖像拒絕MOPLL |
| 文件頁數(shù)： | 21/27頁 |
| 文件大?。?/td> | 593K |
| 代理商： | SL2610LH1Q |
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SL2610
Data Sheet
21
Zarlink Semiconductor Inc.
Characteristic
Pin
Min.
Typ.
Max.
Units
Conditions
IFAMP
Input frequency range
32
60
MHz
Input impedance
200
Differential, see Figure 16.
Gain
20
18.5
24
22.5
dB
dB
At 36 MHz and 44 MHz IF frequency.
At 57 MHz IF frequency.
Voltage conversion gain from 200
differential source to differential load
as contained in Figure 7, see Note 3.
Output impedance
100
Differential, see Figure 17.
Output limiting
3
2.7
Vp-p
Vp-p
At 36 MHz and 44 MHz IF fequency.
At 57 MHz IF frequency.
Differential into load as in Figure 7.
IFAMP OPIP3
135
dB
μ
V
Two output tones at 2 MHz separation
at 104 dBuV into load as in Figure 7,
see Note 2.
IFAMP OPIM3
-62
dBc
Two output tones at 2 MHz separation
at 104 dBuV into load as in Figure 7,
see Note 2.
AGCBIAS Leakage
current
28
-100
-50
100
50
μ
A
μ
A
Vee
≤
Vagc1
≤
Vcc
1.5V
≤
Vagc1
≤
3.5V
AGCOUT voltage
range
13
0.5
3
V
Max load current 20
μ
A.
AGC output level set
See Figure 18.
Supply rejection
-52
dBc
Spurs introduced on converted output
relative to desired signal by a supply
ripple voltage of 10 mV p-p in the
range 1 kHz to 100 kHz (including
external supply decoupling).
Synthesiser
SDA, SCL
Input high voltage
Input low voltage
Input current
Leakage current
Hysterysis
19, 20
19, 20
3
0
-10
0.4
5.5
1.5
10
10
V
V
μ
A
μ
A
V
Input voltage =Vee to Vcc
Input voltage = Vee to 5.5 V, Vcc=Vee
SDA output voltage
19
0.4
0.6
V
V
Isink = 3 mA
Isink = 6 mA
SCL clock rate
20
400
kHz
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