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參數(shù)資料
| 型號： | SL2610 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Wide Dynamic Range Image Reject MOPLL |
| 中文描述： | 寬動態(tài)范圍圖像拒絕MOPLL |
| 文件頁數(shù)： | 5/27頁 |
| 文件大小： | 593K |
| 代理商： | SL2610 |
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SL2610
Data Sheet
5
Zarlink Semiconductor Inc.
1.0 Functional Description
The SL2610 is a multi band RF mixer oscillator with image reject and on-board frequency synthesizer. It is intended
primarily for application in all band terrestrial tuners and requires a minimum external component count. It contains
all elements required for RF downconversion to a standard IF with the exception of external VCO tank circuits.
The pin allocation is contained in Figure 2 and the block diagram in Figure 1.
1.1 Mixer/oscillator section
In normal application the RF input is interfaced to the selected mixer oscillator preamplifier through the tuner
prefilter and AGC stages. The mixer input is arranged such that the signal can be coupled either differentially or
single-ended, and achieves the specified minimum performance in both configurations. Band input impedances
and NF are contained in Figure 11 and Figure 12 respectively. The converter two tone input spectra are contained
in Figure 13 and Figure 14.
The preamplifier output then feeds the mixer stage where the required channel is image reject downconverted to
the IF frequency. The local oscillator frequency for the downconversion is obtained from the on board local
oscillator, which uses an external varactor tuned tank. Typical VCO applications are contained in Figures 8, 9 and
10.
The output of the mixer is then fed to the converter output driver which presents a matched 200
differential load
to an external IF shaping filter.
The output of the shaping filter is then coupled into the IFAMP stage, which provides further gain and offers a 50
output impedance to interface direct with the tuner SAW filter.
The SL2610 contains a broadband level detect circuit whose output can be used to control the tuner AGC. The
target level of the AGC detector is controlled by the voltage applied to the AGCBIAS pin. The characteristic of the
target level is given in Figure 18.
1.2 PLL Frequency Synthesizer
The PLL frequency synthesizer section contains all the elements necessary, with the exception of a frequency
reference and loop filter, to control a varicap tuned local oscillator, so forming a complete PLL frequency
synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high
speed logic, which enables the generation of a loop with good phase noise performance. It can also be operated
with comparison frequencies appropriate for frequency offsets as required in digital terrestrial (DTT) receivers.
The LO signal is multiplexed from the selected oscillator section to an internal preamplifier which provides gain and
reverse isolation from the divider signals. The output of the preamplifier interfaces direct with the 15-bit fully
programmable divider which is of MN+A architecture, where the dual modulus prescaler is 16/17, the A counter is
4-bits and the M counter is 11 bits.
The output of the programmable divider is fed to the phase comparator where it is compared in both phase and
frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal
controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to
the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in Table 1.
The output of the phase detector feeds a charge pump and loop amplifier section which when used with an external
loop filter integrates the current pulses into the varactor line voltage.
The programmable divider output Fpd, divided by two and the reference divider output Fcomp, can be switched to
port P0 by programming the device into test mode. The test modes are described in Table 5.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SL2610IG | Wide Dynamic Range Image Reject MOPLL |
| SL2610LH1N | Wide Dynamic Range Image Reject MOPLL |
| SL2610LH1Q | Wide Dynamic Range Image Reject MOPLL |
| SL2610LH2N | Wide Dynamic Range Image Reject MOPLL |
| SL2610LH2Q | Wide Dynamic Range Image Reject MOPLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SL2610IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Wide Dynamic Range Image Reject MOPLL |
| SL2610LH1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Wide Dynamic Range Image Reject MOPLL |
| SL2610LH1Q | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Wide Dynamic Range Image Reject MOPLL |
| SL2610LH2N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Wide Dynamic Range Image Reject MOPLL |
| SL2610LH2Q | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Wide Dynamic Range Image Reject MOPLL |
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