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參數資料
| 型號： | SIW3500GIG3SR |
| 廠商： | RF MICRO DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA96 |
| 封裝： | 6 X 6 MM, GREEN, VFBGA-96 |
| 文件頁數： | 26/28頁 |
| 文件大?。?/td> | 795K |
| 代理商： | SIW3500GIG3SR |
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Preliminary
7 of 28
SiW3500
60 0066 R00JIrf SiW3500 UltimateBlue SoC DS
Pin Description
The following table provides detailed listings of pin descriptions arranged by functional groupings.
Name
Pad Type
Ball
Bump
See Note 1
Description
Radio (Power from VCC)
RF_IO
Analog
A2
92
RF signal. Input and output.
TX_BIAS
Analog
A4
89
Internal transmitter driver bias.
VTUNE
Analog
A6
85
Pin for reference PLL loop filter, only used if reference fre-
quency is not integer multiples of 4 MHz.
CHG_PUMP
Analog
F1
10
Pin for RF loop filter.
XTAL_N
Analog
B7
82
System clock crystal negative input. If a reference clock is
used, this pin should be left unconnected.
XTAL_P/CLK
Analog
A7
83
System clock crystal positive input or reference clock input.
IDAC
Analog
B1
1
Power control to external power amplifier. This output pro-
vides a variable current source that can be used to control the
external power amp. Leave unconnected if not used.
VREFN_CAP
Analog
C2
3
Decoupling capacitor for internal A/D converter voltage refer-
ence.
VREFP_CAP
Analog
C1
2
Decoupling capacitor for internal A/D converter voltage refer-
ence.
Low Power Oscillator and Reset (Power from VDD_P_ALT)
CLK32K_IN
Analog
L1
21
For crystal or external clock input (32.768 kHz).
CLK32K_OUT
Analog
K1
20
Drive for crystal.
RESET_N
CMOS input
G1
12
System level reset (active low).
Power Control Interface (Power from VDD_P)
AUX_TXD
CMOS bi-directional
G9
58
Auxiliary UART serial port output.
Multi-function (MFP) I/O (Power from VDD_P_ALT)
MFP [0]
CMOS bi-directional
F3
15
Multi-function I/O port.
MFP [1]
CMOS bi-directional
J1
17
Multi-function I/O port.
PWR_REG_EN
CMOS bi-directional
G2
14
CLOCK_REQ_OUT control line for external TCXO by default,
or can be used as enable for an external voltage regulator.
Programmable active high or active low.
ADC_IN
Analog
J2
19
Analog to digital converter input or FREQ_SEL_(0).
Multi-function (MFP) I/O (Power from VDD_P)
MFP [2]
CMOS bi-directional
L6
35
Multi-function I/O port.
MFP [3]
CMOS bi-directional
F10
59
Multi-function I/O port.
MFP [4]
CMOS bi-directional
B9
76
Multi-function I/O port.
MFP [5]
CMOS bi-directional
C8
77
Multi-function I/O port.
MFP [6]
CMOS bi-directional
C7
80
Multi-function I/O port.
MFP [7]
CMOS bi-directional
C6
81
Multi-function I/O port.
PCM Interface (Power from VDD_P_ALT)
PCM_IN
CMOS bi-directional
H3
28
PCM data output from SiW3500.
PCM_OUT
CMOS bi-directional
L2
23
PCM data input to SiW3500.
PCM_CLK
CMOS bi-directional
K3
25
PCM synchronous data clock to the remote device. Normally
an output. Input for slave mode.
PCM_SYNC
CMOS bi-directional
K2
22
PCM synchronization data strobe to the remote device. Nor-
mally an output. Input for slave mode.
Table 1. SiW3500 SoC Pin List
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| SIW73 | 制造商:DELTA 制造商全稱:Delta Electronics, Inc. 功能描述:SMT Power Inductor |
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| SIW73-101 | 制造商:DELTA 制造商全稱:Delta Electronics, Inc. 功能描述:SMT Power Inductor |
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| SIW73-150 | 制造商:DELTA 制造商全稱:Delta Electronics, Inc. 功能描述:SMT Power Inductor |
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