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參數(shù)資料
| 型號： | SI5364 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SONET/SDH PRECISION PORT CARD CLOCK IC |
| 中文描述： | SONET / SDH的精密端口卡時(shí)鐘IC |
| 文件頁數(shù)： | 32/40頁 |
| 文件大?。?/td> | 565K |
| 代理商： | SI5364 |
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Si5364
32
Rev. 2.2
H1
SYNCIN
I*
LVTTL
Synchronization Input for Frame Sync Clock.
Allows time alignment/realignment of the FSYNC
output clock. A rising edge on the SYNCIN input
forces alignment of the FSYNC output clock stream.
H2
DSBLFSYNC
I*
LVTTL
Disable the FSYNC Clock Output.
When high, the output driver for the FSYNC pin is
disabled.
A3
B3
FEC[0]
FEC[1]
I*
LVTTL
Forward Error Correction (FEC) Selection.
Enable or disable scaling of the input-to-output fre-
quency multiplication factor for FEC clock rate com-
patibility.
The multiplication ratios and associated frequency
ranges for the Si5364 clock outputs are set by the
FRQSEL pins associated with each clock output.
Additional scaling by a factor of either 255/238 or
238/255 can be applied to all active outputs as indi-
cated below.
The FEC[1:0] inputs are decoded as follows:
00 = No FEC scaling, FSYNC enabled.
01 = 255/238 FEC scaling for all clock outputs,
FSYNC disabled.
10 = 238/255 FEC scaling for all clock inputs,
FSYNC enabled.
11 = Reserved.
The FSYNC output is disabled when FEC[1:0] = 01.
A2
B2
BWSEL[0]
BWSEL[1]
I*
LVTTL
Bandwidth Select.
The BWSEL[1:0] pins set the bandwidth of the loop
filter within the DSPLL to 3200 Hz, 800 Hz, or
6400 Hz as indicated below.
00 = 3200 Hz
01 = 1600 Hz
10 = 800 Hz
11 = 6400 Hz
B10
CAL_ACTV
O
LVTTL
Calibration Mode Active.
Is driven high during the DSPLL self-calibration and
the subsequent initial lock acquisition period.
C7–9, D1–2,
F1–2
Rsvd_GND
—
LVTTL
Reserved—Tie to Ground.
Must be tied to GND for normal operation.
B6–8, C6
Rsvd_NC
—
LVTTL
Reserved—No Connect.
Must be left unconnected for normal operation.
Table 10. Pin Descriptions (Continued)
I/O
Signal Level
Pin #
Pin Name
Description
*Note:
The LVTTL inputs on the Si5364 device have an internal pulldown mechanism that causes the input to default to a logic
low state if the input is not driven from an external source.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5364BC | 制造商:SILICON 功能描述: |
| SI5364-EVB | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Multi/Jitter/Hitless 19 55 622MHz Out RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5364FBC | 制造商:Vishay Siliconix 功能描述: |
| SI5364-F-BC | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Multi/Jitter/Hitless 19 55 622MHz Outpt RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5364-G-BC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Precision Port Card 19 155 622 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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