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參數資料
| 型號： | SI5364 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SONET/SDH PRECISION PORT CARD CLOCK IC |
| 中文描述： | SONET / SDH的精密端口卡時鐘IC |
| 文件頁數： | 31/40頁 |
| 文件大?。?/td> | 565K |
| 代理商： | SI5364 |
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Si5364
Rev. 2.2
31
K4
K3
CLKOUT_1+
CLKOUT_1–
O
CML
Differential Clock Output 1.
High-frequency output clock derived from the
selected reference source (CLKIN_A, CLKIN_B, or
REF/CLKIN_F) or from Digital hold mode.
The frequencies of the Si5364 clock outputs are
each 1, 8, or 32x multiple of the frequency of the
selected clock input. The multiplication ratio is
selected using Frequency Select (FRQSEL) control
pins associated with each clock output. An additional
scaling factor of either 238/255 or 255/238 can be
selected for FEC operation using the FEC[1:0] con-
trol pins.
K6
K7
CLKOUT_2+
CLKOUT_2–
O
CML
Differential Clock Output 2.
See CLKOUT_1.
K10
K9
CLKOUT_3–
O
CML
Differential Clock Output 3.
See CLKOUT_1.
H10
G10
CLKOUT_4+
CLKOUT_4–
O
CML
Clock Output 4.
See CLKOUT_1.
J3
J4
FRQSEL_1[0]
FRQSEL_1[1]
I*
LVTTL
Frequency Select—Clock Out 1.
Selects the multiplication factor between the fre-
quency of the selected clock input and the frequency
of the clock output.
The FRQSEL_1[1:0] inputs are decoded as follows:
00 = Clock Driver Power Down.
01 = 1x multiplication (19.44 MHz output typical).
10 = 8x multiplication (155.52 MHz output typical).
11 = 32x multiplication (622.08 MHz output typical.
The clock output multiplication ratios can be scaled
additionally by a factor of 255/238 or 238/255 for
FEC operation. See FEC[1:0] pin description.
J6
J7
FRQSEL_2[0]
FRQSEL_2[1]
I*
LVTTL
Frequency Select—Clock Out 2.
See FRQSEL_1[1:0].
J10
J9
FRQSEL_3[0]
FRQSEL_3[1]
I*
LVTTL
Frequency Select—Clock Out 3.
See FRQSEL_1[1:0].
G9
H9
FRQSEL_4[0]
FRQSEL_4[1]
I*
LVTTL
Frequency Select—Clock Out 4.
See FRQSEL_1[1:0].
J1
FSYNC
O
See Table 3
Frame Sync Clock.
Nominally 8 kHz based on a 19.44 MHz reference.
The 8 kHz frame sync is disabled when 255/238 FEC
scaling of the clock output frequencies is selected.
See FEC[1:0] pin description.
Table 10. Pin Descriptions (Continued)
I/O
Signal Level
Pin #
Pin Name
Description
*Note:
The LVTTL inputs on the Si5364 device have an internal pulldown mechanism that causes the input to default to a logic
low state if the input is not driven from an external source.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SI5364BC | 制造商:SILICON 功能描述: |
| SI5364-EVB | 功能描述:時鐘和定時器開發(fā)工具 Multi/Jitter/Hitless 19 55 622MHz Out RoHS:否 制造商:Texas Instruments 產品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5364FBC | 制造商:Vishay Siliconix 功能描述: |
| SI5364-F-BC | 功能描述:時鐘合成器/抖動清除器 Multi/Jitter/Hitless 19 55 622MHz Outpt RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5364-G-BC | 功能描述:時鐘發(fā)生器及支持產品 SONET/SDH Precision Port Card 19 155 622 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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