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參數(shù)資料
| 型號： | SI5364-F-BC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SONET/SDH PRECISION PORT CARD CLOCK IC |
| 中文描述： | SONET / SDH的精密端口卡時鐘IC |
| 文件頁數(shù)： | 34/40頁 |
| 文件大?。?/td> | 565K |
| 代理商： | SI5364-F-BC |
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Si5364
34
Rev. 2.2
C3
INCDELAY
I*
LVTTL
Increment Output Phase Delay.
The INCDELAY and DECDELAY pins can adjust the
phase of the Si5364 clock outputs. Adjustment is
accomplished by driving a pulse (a transition from
low to high and then back to low) into one of the pins
while the other pin is held at a logic low level.
Each pulse on the INCDELAY pin adds a fixed delay
to the Si5364’s clock outputs. The fixed delay time is
equal to twice the period of the 622 MHz output clock
(t
DELAY
= 2/f
o_622
). The frequency of the 622 MHz
output clock (f
o_622
)
is nominally 32x the frequency of
the input clock. The frequency of the 622 MHz output
clock (fo_622) is scaled additionally according to the
setting of the FEC[1:0] pins.
When the phase of the Si5364 clock outputs is
adjusted using the INCDELAY and/or DECDELAY
pins, the output clock moves to its new phase setting
at a rate of change that is determined by the setting
of the BWSEL[1:0] pins.
Note:
INCDELAY is ignored when the Si5364 is operating
in digital hold (DH) mode.
C4
DECDELAY
I*
LVTTL
Decrement Output Phase Delay.
The INCDELAY and DECDELAY pins can adjust the
phase of the Si5364 clock outputs. Adjustment is
accomplished by driving a pulse (a transition from
low to high and then back to low) into one of the pins
while the other pin is held at a logic low level.
Each pulse on the DECDELAY pin removes a fixed
delay from the Si5364’s clock outputs. The fixed
delay time is equal to twice the period of the 622
MHz output clock (t
DELAY
= 2/f
o_622
). The frequency
of the 622 MHz output clock (f
o_622
)
is nominally 32x
the frequency of the input clock. The frequency of the
622 MHz output clock (fo_622) is scaled additionally
according to the setting of the FEC[1:0] pins.
When the phase of the Si5364 clock outputs is
adjusted using the INCDELAY and/or DECDELAY
pins, the output clock moves to its new phase setting
at a rate of change that is determined by the setting
of the BWSEL[1:0] pins.
Note:
INCDELAY is ignored when the Si5364 is operating
in digital hold (DH) mode.
Table 10. Pin Descriptions (Continued)
I/O
Signal Level
Pin #
Pin Name
Description
*Note:
The LVTTL inputs on the Si5364 device have an internal pulldown mechanism that causes the input to default to a logic
low state if the input is not driven from an external source.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5364-G-BC | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Precision Port Card 19 155 622 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5364-H-BL | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Prcsn Port Card Clock Multiplr RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5364-H-BLR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Precision 19MHz 155MHz 622MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5364-H-GL | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Prcsn Port Card Clock Multiplr RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5364-H-GLR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Precision 19MHz 155MHz 622MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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