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參數(shù)資料
| 型號(hào)： | SI5320-X-BC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SONET/SDH PRECISION CLOCK MULTIPLIER IC |
| 中文描述： | SONET / SDH的精密時(shí)鐘倍頻集成電路 |
| 文件頁(yè)數(shù)： | 26/34頁(yè) |
| 文件大?。?/td> | 538K |
| 代理商： | SI5320-X-BC |
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Si5320
26
Rev. 2.3
H6
H7
CLKOUT+
CLKOUT–
O
CML
Differential Clock Output.
High frequency clock output. The frequency of the
CLKOUT output is a multiple of the frequency of the
CLKIN input. The input-to-output frequency multipli-
cation factor is set by selecting the clock input range
and the clock output range. The frequency of the
CLKOUT clock output can be in the 19, 155, or
622 MHz range as indicated in Table 3 on page 7.
The clock output frequency is selected using the
FRQSEL[1:0] pins. The clock input frequency is
selected using the INFRQSEL[2:0] pins. An addi-
tional scaling factor of either 255/238 or 238/255
may be selected for FEC operation using the
FEC[1:0] control pins.
H5
H8
FRQSEL[0]
FRQSEL[1]
I*
LVTTL
Clock Output Frequency Range Select
Select frequency range of the clock output, CLK-
OUT. (See Table 3 on page 7.)
00 = Clock Driver Powerdown.
01 = 19 MHz Frequency Range.
10 = 155 MHz Frequency Range.
11 = 622 MHz Frequency Range.
A3
A2
FEC[0]
FEC[1]
I*
LVTTL
Forward Error Correction (FEC) Selection.
Enable or disable scaling of the input-to-output fre-
quency multiplication factor for FEC clock rate com-
patibility.
The frequency of the CLKOUT output is a multiple of
the frequency of the CLKIN input. The input-to-out-
put frequency multiplication factor is set by selecting
the clock input range and the clock output range.
The clock output frequency is selected using the
FRQSEL[1:0] pins. The clock input frequency is
selected using the INFRQSEL[2:0] pins. An addi-
tional scaling factor of either 255/238 or 238/255
may be selected for FEC operation using the
FEC[1:0] control pins as indicated below.
00 = No FEC scaling.
01 = 255/238 FEC scaling for all clock outputs.
10 = 238/255 FEC scaling for all clock inputs.
11 = Reserved.
Note:
FEC[1:0] must be set to 00 when DBLBW is set
high.
Table 11. Si5320 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
*Note:
The LVTLL inputs on the Si5320 device have an internal pulldown mechanism that causes these inputs to default to a
logic low state if the input is not driven from an external source.
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