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參數(shù)資料
| 型號： | SI5318 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SONET/SDH PRECISION CLOCK MULTIPLIER IC |
| 中文描述： | SONET / SDH的精密時鐘倍頻集成電路 |
| 文件頁數(shù)： | 17/30頁 |
| 文件大?。?/td> | 593K |
| 代理商： | SI5318 |
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Si5318
Rev. 1.0
17
The Si5318 also provides an output indicating the digital
hold status of the device, DH_ACTV. The Si5318 only
enters the digital hold mode upon the loss of the input
clock. When this occurs, the LOS alarm will also be
active. Therefore, applications that require monitoring of
the status of the Si5318 need only monitor the
CAL_ACTV and either the LOS or DH_ACTV outputs to
know the state of the device.
2.7. Reset
The Si5318 provides a Reset/Calibration pin, RSTN/
CAL, which resets the device and disables the outputs.
When the RSTN/CAL pin is driven low, the internal
circuitry enters into the reset mode, and all LVTTL
outputs are forced into a high-impedance state. Also,
the CLKOUT+ and CLKOUT– pins are forced to a
nominal CML logic LOW and HIGH respectively (See
Figure 9). This feature is useful in in-circuit test
applications. A low-to-high transition on RSTN/CAL
initializes all digital logic to a known condition and
initiates self-calibration of the DSPLL. Upon completion
of self-calibration, the DSPLL begins to lock to the clock
input signal.
Figure 9. CLKOUT± Equivalent Circuit, RSTN/
CAL asserted LOW
2.8. PLL Self-Calibration
The Si5318 achieves optimal jitter performance by
using self-calibration circuitry to set the VCO center
frequency and loop gain parameters within the DSPLL.
Internal circuitry generates self calibration automatically
on powerup or after a loss of power condition. Self-
calibration can also be manually initiated by a low-to-
high transition on the RSTN/CAL input.
Whether manually initiated or automatically initiated at
powerup, the self-calibration process requires the
presence of a valid input clock.
If the self-calibration is initiated without a valid clock
present, the device waits for a valid clock before
completing the self-calibration. The Si5318 clock output
is set to the lower end of the operating frequency range
while the device is waiting for a valid clock. After the
clock input is validated, the calibration process runs to
completion; the device locks to the clock input, and the
clock output shifts to its target frequency. Subsequent
losses of the input clock signal do not require re-
calibration. If the clock input is lost following self-
calibration, the device enters digital hold mode. When
the input clock returns, the device re-locks to the input
clock without performing a self-calibration. During the
calibration process, the output clock frequency is
indeterminate and may jump as high as 5% above the
final locked value.
2.9. Bias Generation Circuitry
The Si5318 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces power consumption and variation as compared
with traditional implementations that use an internal
resistor. The bias generation circuitry requires a 10 k
(1%) resistor connected between REXT and GND.
2.10. Differential Input Circuitry
The Si5318 provides a differential input for the clock
input, CLKIN. This input is internally biased to a voltage
of V
ICM
(see Table 2 on page 6) and may be driven by a
differential or single-ended driver circuit. For differential
transmission lines, the termination resistor is connected
externally as shown.
2.11. Differential Output Circuitry
The Si5318 utilizes a current mode logic (CML)
architecture to drive the differential clock output,
CLKOUT.
For single-ended output operation, simply connect to
either CLKOUT+ or CLKOUT–, and leave the unused
signal unconnected.
2.12. Power Supply Connections
The Si5318 incorporates an on-chip voltage regulator.
The
voltage
regulator
compensation circuit of one resistor and one capacitor
to ensure stability over all operating conditions.
Internally, the Si5318 V
DD33
pins are connected to the
on-chip voltage regulator input, and the V
DD33
pins also
supply power to the device’s LVTTL I/O circuitry. The
V
DD25
pins supply power to the core DSPLL circuitry
and are also used for connection of the external
compensation circuit.
requires
an
external
100
V
DD
2.5 V
100
CLKOUT–
CLKOUT+
15 mA
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SI5318-EVB | 功能描述:時鐘和定時器開發(fā)工具 SI5318 EVALUATION BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5318-F-BC | 功能描述:時鐘合成器/抖動清除器 SONET/SDH PRECISION CLOCK MULT.IC 19/155 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5318-F-BCR | 功能描述:IC MULTIPLIER SONET/SDH 63CBGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:DSPLL® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SI5318-G-BC | 功能描述:電信集成電路 SONET/SDH Precision Clock Multiplier IC RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| SI5319 | 制造商:SILABS 制造商全稱:SILABS 功能描述:ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR |
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