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參數(shù)資料
| 型號： | SI5318 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SONET/SDH PRECISION CLOCK MULTIPLIER IC |
| 中文描述： | SONET / SDH的精密時鐘倍頻集成電路 |
| 文件頁數(shù)： | 15/30頁 |
| 文件大?。?/td> | 593K |
| 代理商： | SI5318 |
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Si5318
Rev. 1.0
15
2.3. PLL Performance
The Si5318 PLL is designed to provide extremely low
jitter generation, high jitter tolerance, and a well-
controlled jitter transfer function with low peaking and a
high degree of jitter attenuation.
2.3.1. Jitter Generation
Jitter generation is defined as the amount of jitter
produced at the output of the device with a jitter free
input clock. Generated jitter arises from sources within
the VCO and other PLL components. Jitter generation is
also a function of the PLL bandwidth setting. Higher
loop bandwidth settings may result in lower jitter
generation, but may also result in less attenuation of
jitter on the input clock signal.
2.3.2. Jitter Transfer
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter for a specified jitter frequency. The
jitter transfer characteristic determines the amount of
input clock jitter that passes to the outputs. The DSPLL
technology used in the Si5318 provides tightly-
controlled jitter transfer curves because the PLL gain
parameters are determined by digital circuits that do not
vary over supply voltage, process, and temperature. In
a system application, a well-controlled transfer curve
minimizes the output clock jitter variation from board to
board, providing more consistent system level jitter
performance.
The jitter transfer characteristic is a function of the
BWSEL[1:0] setting. (See Table 7.) Lower bandwidth
selection settings result in more jitter attenuation of the
incoming clock but may result in higher jitter generation.
Table 4 on page 8 gives the 3 dB bandwidth and
peaking values for specified BWSEL settings. Figure 6
shows the jitter transfer curve mask.
Figure 6. PLL Jitter Transfer Mask/Template
Table 7. Loop Bandwidth Settings
Loop
Bandwidth
BWSEL1
BWSEL0
DBLBW
*
12800 Hz
1
1
1
6400 Hz
1
1
0
6400 Hz
0
0
1
3200 Hz
0
0
0
3200 Hz
0
1
1
1600 Hz
0
1
0
1600 Hz
1
0
1
800 Hz
1
0
0
*Note:
When DBLBW = 1, FXDDELAY must be asserted.
Table 8. Nominal Clock Input Frequencies
Input Clock
Frequency
Range
Reserved
Reserved
Reserved
155 MHz
78 MHz
39 MHz
19 MHz
Reserved
INFRQSEL2
INFRQSEL1
INFRQSEL0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Table 9. Nominal Clock Output Frequencies
Output Clock Frequency
Range
Reserved
155 MHz
19 MHz
Driver Powerdown
FRQSEL1
FRQSEL0
1
1
0
0
1
0
1
0
Jitter
Transfer
0 dB
F
BW
f
Jitter
Peaking
–20 dB/dec.
Jitter Out
Jitter In
(s)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SI5318-EVB | 功能描述:時鐘和定時器開發(fā)工具 SI5318 EVALUATION BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5318-F-BC | 功能描述:時鐘合成器/抖動清除器 SONET/SDH PRECISION CLOCK MULT.IC 19/155 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5318-F-BCR | 功能描述:IC MULTIPLIER SONET/SDH 63CBGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:DSPLL® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SI5318-G-BC | 功能描述:電信集成電路 SONET/SDH Precision Clock Multiplier IC RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| SI5319 | 制造商:SILABS 制造商全稱:SILABS 功能描述:ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR |
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