參數資料
型號: SI5010
廠商: Electronic Theatre Controls, Inc.
英文描述: OC-12/3, STM-4/1 SONET/SDH CLOCK AND DATA RECOVERY IC
中文描述: 的OC - 12 / 3接口,STM - 4 / 1的SONET / SDH時鐘和數據恢復芯片
文件頁數: 6/16頁
文件大?。?/td> 287K
代理商: SI5010
Si5010
6
Preliminary Rev. 0.31
Table 2. DC Characteristics
(V
DD
= 2.5 V ± 5%, T
A
= –40°C to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply Current
OC-12
OC-3
I
DD
117
124
127
134
mA
Power Dissipation
OC-12
OC-3
P
D
293
310
333
352
mW
Common Mode Input Voltage (DIN,
REFCLK)
V
ICM
varies with V
DD
.80
"
V
DD
V
Input Voltage Range* (DIN+, DIN–,
REFCLK+, REFCLK–)
V
IS
See Figure 2
750
mV
Differential Input Voltage Swing*
(DIN, REFCLK)
V
ID
See Figure 2
200
1500
mV
(pk-pk)
Input Impedance (DIN, REFCLK)
R
IN
V
OD
Line-to-Line
84
100
116
Differential Output Voltage Swing
(DOUT)
100
Load
Line-to-Line
TBD
940
TBD
mV
(pk-pk)
Differential Output Voltage Swing
(CLKOUT)
V
OD
100
Load
Line-to-Line
TBD
900
TBD
mV
(pk-pk)
Output Common Mode Voltage
(DOUT,CLKOUT)
V
OCM
100
Load
Line-to-Line
V
DD
– 0.7
V
Output Impedance (DOUT,CLKOUT)
R
OUT
I
SC(–)
I
SC(+)
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
R
IN
I
PWRDN
Single-ended
84
100
116
Output Short to GND (DOUT,CLKOUT)
25
TBD
mA
Output Short to V
DD
(DOUT,CLKOUT)
Input Voltage Low (LVTTL Inputs)
TBD
–15
mA
.8
V
Input Voltage High (LVTTL Inputs)
2.0
V
Input Low Current (LVTTL Inputs)
10
μ
A
Input High Current (LVTTL Inputs)
10
μ
A
Output Voltage Low (LVTTL Outputs)
I
O
= 2 mA
I
O
= 2 mA
0.4
V
Output Voltage High (LVTTL Outputs)
2.0
V
Input Impedance (LVTTL Inputs)
10
k
PWRDN/CAL Leakage Current
V
PWRDN
0.8 V
TBD
25
TBD
μ
A
*Note:
The DIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage
swing of the signal applied to the active input must exceed the specified minimum Differential Input Voltage Swing (V
ID
min) and the unused input must be tied to ground. When driving differentially, the difference between the positive and
negative input signals must exceed V
ID
min. (Each individual input signal needs to swing only half of this range.) In
either case, the voltage applied to any individual pin (DIN+, DIN–, REFCLK+, or REFCLK–) must not exceed the
specified maximum Input Voltage Range (V
IS
max).
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