參數(shù)資料
型號(hào)： Si5010-BM
廠商： Electronic Theatre Controls, Inc.
英文描述： OC-12/3, STM-4/1 SONET/SDH CLOCK AND DATA RECOVERY IC
中文描述： 的OC - 12 / 3接口，STM - 4 / 1的SONET / SDH時(shí)鐘和數(shù)據(jù)恢復(fù)芯片
文件頁(yè)數(shù)： 10/16頁(yè)
文件大?。?/td> 287K
代理商： SI5010-BM
Si5010
10
Preliminary Rev. 0.31
Figure 6. Jitter Tolerance Specification
Jitter Transfer
The Si5010 is fully compliant with the relevant Bellcore/
ITU specifications related to SONET/SDH jitter transfer.
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter as a function of jitter frequency (see
Figure 7). These measurements are made with an input
test signal that is degraded with sinusoidal jitter whose
magnitude is defined by the mask in Figure 6.
Jitter Generation
The Si5010 meets all relevant specifications for jitter
generation proposed for SONET/SDH equipment. The
jitter generation specification defines the amount of jitter
that may be present on the recovered clock and data
outputs when a jitter free input signal is provided. The
Si5010 typically generates less than 1.6 mUI
RMS
of jitter
when presented with jitter-free input data.
Figure 7. Jitter Transfer Specification
Power Down
The Si5010 provides a power down pin, PWRDN/CAL,
that disables the device. When the PWRDN/CAL pin is
driven “high”, the positive and negative terminals of
CLKOUT and DOUT are each tied to VDD through
100
on-chip resistors. This feature is useful in
reducing power consumption in applications that
employ redundant serial channels. When PWRDN/CAL
is released (set to “l(fā)ow”) the digital logic resets to a
known initial condition, recalibrates the DSPLL, and will
begin to lock to the data stream.
Note:
LOL is not asserted when the device is in the power
down state.
Device Grounding
The Si5010 uses the GND pad on the bottom of the
20-pin micro leaded package (MLP) for device ground.
This pad should be connected directly to the analog
supply ground. See Figures 10 and 11 for the ground
(GND) pad location.
Bias Generation Circuitry
The Si5010 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces
power
consumption
implementations that use an internal resistor. The bias
generation circuitry requires a 10 k
(1%) resistor
connected between REXT and GND.
versus
traditional
f0
f1
f2
f3
ft
Frequency
0.15
1.5
15
Sinusoidal
Input
Jitter (UI p-p)
Slope = 20 dB/Decade
SONET
Data Rate
F0
(Hz)
F1
(Hz)
F2
(Hz)
F3
(kHz)
Ft
(kHz)
OC-12
OC-3
10
10
30
30
300
300
25
6.5
250
65
Fc
Frequency
Jitter
Transfer
0.1 dB
Acceptable
Range
20 dB/Decade
Slope
SONET
Data Rate
OC-12
OC-3
Fc
(kHz)
500
130
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SI5010-BMR 功能描述:計(jì)時(shí)器和支持產(chǎn)品 SONET/SDH 2.5 V OC-3/12 STM-1/4 RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel
SI5010-EVB 功能描述:時(shí)鐘和定時(shí)器開(kāi)發(fā)工具 SONET/SDH 2.5 V OC-3/12 STM-1/4 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
SI5010-GM 制造商:SILABS 制造商全稱:SILABS 功能描述:OC-12/3, STM-4/1 SONET/SDH CLOCK AND DATA RECOVERY IC
SI5010-GMR 制造商:Silicon Laboratories Inc 功能描述:
SI-50112 制造商:BEL 制造商全稱:Bel Fuse Inc. 功能描述:SI-50112
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