參數(shù)資料
型號(hào)： Si4113-BT
廠商： Electronic Theatre Controls, Inc.
英文描述： DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS FOR WIRELESS COMMUNICATIONS
中文描述： 雙波段射頻合成器集成的無(wú)線通信和VCO
文件頁(yè)數(shù)： 16/34頁(yè)
文件大?。?/td> 713K
代理商： SI4113-BT
Si4133
16
Rev. 1.1
Functional Description
The Si4133 is a monolithic integrated circuit that
performs IF and dual-band RF synthesis for wireless
communications applications. This integrated circuit
(IC), with minimal external components, completes the
frequency synthesis function necessary for RF
communications systems.
The Si4133 has three complete phase-locked loops
(PLLs) with integrated voltage-controlled oscillators
(VCOs). The low phase noise of the VCOs makes the
Si4133 suitable for use in demanding wireless
communications applications. Phase detectors, loop
filters, and reference and output frequency dividers are
integrated. The IC is programmed through a three-wire
serial interface.
Two PLLs are provided for dual-band RF synthesis.
These RF PLLs are multiplexed so that only one PLL is
active at a given time (as determined by the setting of
an internal register). The active PLL is the last one
written. The center frequency of the VCO in each PLL is
set by the value of an external inductance. Inaccuracies
in these inductances are compensated for by the self-
tuning algorithm. The algorithm is run following power-
up or following a change in the programmed output
frequency.
Each RF PLL, when active, can adjust the RF output
frequency by ±5% of its VCO’s center frequency.
Because the two VCOs can be set to have widely
separated center frequencies, the RF output can be
programmed to service two widely separated frequency
bands by simply programming the corresponding N-
Divider. One RF VCO is optimized to have its center
frequency set between 947 MHz and 1.72 GHz, while
the second RF VCO is optimized to have its center
frequency set between 789 MHz and 1.429 GHz.
One PLL is provided for IF frequency synthesis. The
center frequency of this circuit’s VCO is set by
connection of an external inductance. The PLL can
adjust the IF output frequency by ±5% of the VCO
center frequency. Inaccuracies in the value of the
external inductance are compensated for by the
Si4133’s
proprietary
self-tuning
algorithm is initiated each time the PLL is powered-up
(by either the PWDNB pin or by software) and/or each
time a new output frequency is programmed.
The IF VCO can have its center frequency set as low as
526 MHz and as high as 952 MHz. An IF output divider
is provided to divide down the IF output frequencies, if
needed. The divider is programmable, capable of
dividing by 1, 2, 4, or 8.
algorithm.
This
The unique PLL architecture used in the Si4133
produces settling (lock) times that are comparable in
speed to fractional-N architectures without suffering the
high phase noise or spurious modulation effects often
associated with those designs.
Serial Interface
A timing diagram for the serial interface is shown in
Figure 2 on page 7. Figure 3 on page 7 shows the
format of the serial word.
The Si4133 is programmed serially with 22-bit words
comprised of 18-bit data fields and 4-bit address fields.
When the serial interface is enabled (i.e., when SENB is
low) data and address bits on the SDATA pin are
clocked into an internal shift register on the rising edge
of SCLK. Data in the shift register is then transferred on
the rising edge of SENB into the internal data register
addressed in the address field. The serial interface is
disabled when SENB is high.
Table 12 on page 21 summarizes the data register
functions and addresses. The internal shift register will
ignore any leading bits before the 22 required bits.
Setting the VCO Center Frequencies
The PLLs can adjust the IF and RF output frequencies
±5% of the center frequencies of their VCOs. Each
center frequency is established by the value of an
external inductance connected to the respective VCO.
Manufacturing tolerances of ±10% for the external
inductances
are
acceptable.
compensate for inaccuracies in each inductance by
executing a self-tuning algorithm following PLL power-
up or following a change in the programmed output
frequency.
Because the total tank inductance is in the low nH
range, the inductance of the package needs to be
considered in determining the correct external
inductance. The total inductance (L
TOT
) presented to
each VCO is the sum of the external inductance (L
EXT
)
and the package inductance (L
PKG
). Each VCO has a
nominal capacitance (C
NOM
) in parallel with the total
inductance, and the center frequency is as follows:
The
Si4133
will
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