參數(shù)資料
型號(hào)： SI3018
廠商： Allegro MicroSystems, Inc.
英文描述： LOW-VOLTAGE, HIGH-CURRENT 1.8 V LINEAR REGULATOR
中文描述： 低電壓，高電流線性穩(wěn)壓器1.8伏
文件頁數(shù)： 8/102頁
文件大?。?/td> 1407K
代理商： SI3018
Si3056
Si3018/19/10
8
Rev. 1.02
Table 4. AC Characteristics
(V
D
=
3.0 to 3.6 V, T
A
=
0 to 70 °C for K-Grade, see Figure 16 on page 17)
Parameter
Sample Rate
1
PLL Output Clock Frequency
1
Symbol
Test Condition
Min
Typ
Max
Unit
Fs
Fs = F
PLL2
/5120
F
PLL1
= (F
MCLK
x
M)/N
Low –3 dBFS Corner
7.2
—
16
kHz
F
PLL1
—
98.304
—
MHz
Transmit Frequency Response
—
0
—
Hz
Receive Frequency Response
Low –3 dBFS Corner,
FILT = 0
—
5
—
Hz
Receive Frequency Response
Low –3 dBFS Corner,
FILT = 1
9
—
200
—
Hz
Transmit Full Scale Level
2
V
FS
FULL = 0 (0 dBM)
FULL = 1
9
(3.2 dBM)
—
1.1
—
V
PEAK
V
PEAK
V
PEAK
V
PEAK
dB
1.58
Receive Full Scale Level
2,3
V
FS
FULL = 0 (0 dBM)
FULL = 1
9
(3.2 dBM)
1.1
—
1.58
—
Dynamic Range
4,5
DR
ILIM = 0, DCV = 11, DCR = 0,
I
L
= 120 mA, MINI = 00
ILIM = 0, DCV = 00, DCR = 0,
I
L
= 20 mA, MINI = 11
ILIM = 1, DCV = 11, DCR = 0,
I
L
= 60 mA, MINI = 00
ILIM = 0, DCV = 11, DCR = 0,
I
L
= 120 mA, MINI = 00
ILIM = 0, DCV = 00, DCR = 0,
I
L
= 20 mA, MINI = 11
ILIM = 0, DCV = 00, DCR = 0,
I
L
= 20 mA, MINI = 11
ILIM = 1, DCV = 11, DCR = 0,
I
L
= 60 mA, MINI = 00
—
80
—
Dynamic Range
4,5
DR
—
80
—
dB
Dynamic Range
4,5
DR
—
80
—
dB
Transmit Total Harmonic
Distortion
6,7
THD
—
–72
—
dB
Transmit Total Harmonic
Distortion
6,7
THD
—
–78
—
dB
Receive Total Harmonic
Distortion
6,7
THD
—
–78
—
dB
Receive Total Harmonic
Distortion
6,7
THD
—
–78
—
dB
Notes:
1.
See
Figure 25 on page 35.
2.
Measured at TIP and RING with 600
termination at 1 kHz, as shown in Figure 1.
3.
Receive full scale level produces –0.9 dBFS at SDO.
4.
DR
=
20 x log |V
IN
| + 20 x log (RMS signal/RMS noise). Measurement is 300 to 3400 Hz. Applies to both transmit and
receive paths. V
IN
= 1 kHz, –3 dBFS, Fs = 10300 Hz.
5.
When using the Si3010 line-side, the typical DR values will be approximately 10 dB lower.
6.
THD
=
20 x log (RMS distortion/RMS signal). Vin = 1 kHz, –3 dBFS, Fs = 10300 Hz.
7.
When using the Si3010 line-side, the typical THD values will be approximately 10 dB higher.
8.
DR
CID
= 20 x log (rms V
CID
/rms V
IN
) + 20 x log(rms V
IN
/rms noise). V
CID
is the 6 V full scale level for the typical
application circuit in Figure 16. With the enhanced CID circuit, the V
CID
full scale level is 1.5 V peak, and DR
CID
increases to 62 dB.
9.
Available on the Si3019 line-side device only.
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