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SHF-0589 2 Watt HFET
2
EDS-101242 Rev F
522 Almanor Ave., Sunnyvale, CA 94085
Phone: (800) SMI-MMIC
http://www.sirenza.com
Absolute Maximum Ratings
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MTTF is inversely proportional to the device junction
temperature. For junction temperature and MTTF
considerations the bias condition should also
satisfy the following expression:
P
DC
< (T
J
- T
L
) / R
TH
where:
P
DC
= I
* V
(W)
J
= Junction Temperature (°C)
L
= Lead Temperature (pin 4) (°C)
TH
= Thermal Resistance (°C/W)
1. The SHF-0x89 is a depletion mode FET and requires a negative gate voltage. Normal pinchoff variation from part-to-
part precludes the use of a fixed gate voltage for all devices. Active bias circuitry or manual gate bias alignment is
recommended to maintain acceptable performance (RF and thermal).
2. Active bias circuitry is strongly recommended for class A operation (backoff >6dB).
3. For large signal operation (< 6dB backoff) class AB operation is required to maximize the FET’s performance.
Passive gate bias circuitry is generally required to achieve pure class AB performance. This is generally accomplished
using a voltage divider with temperature compensation. Per item 1 above the gate voltage should be aligned for each
device to eliminate the effects of pinchoff process variation.
4. Choose the operating voltage based on the amount of backoff. For large signal operation the drain-source voltage
should be increased to 8V to maximize P1dB. For small signal operation OIP3 may be improved by reducing the voltage
and increasing the current. The recommended application circuit should be re-optimized if the recommended 7V bias
condition is not used. Make sure the quiescent bias condition does not exceed the recommended power dissipation
limit (shown on page 1).
Design Considerations and Trade-offs
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-40
-10
20
Lead Temperature (C)
50
80
110
140
170
Operational (Tj<140C)
ABS MAX (Tj<165C)
Power Derating Curve
NOTRECOMMENDEDFORNEWDESGN