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Rev. 3.0, 04/02, page vi of xxxviii
3.4.2
3.4.3
MMU Functions ..........................................................................................................
3.5.1
MMU Hardware Management .........................................................................
3.5.2
MMU Software Management...........................................................................
3.5.3
MMU Instruction (LDTLB).............................................................................
3.5.4
Hardware ITLB Miss Handling........................................................................
3.5.5
Avoiding Synonym Problems ..........................................................................
MMU Exceptions.........................................................................................................
3.6.1
Instruction TLB Multiple Hit Exception...........................................................
3.6.2
Instruction TLB Miss Exception......................................................................
3.6.3
Instruction TLB Protection Violation Exception...............................................
3.6.4
Data TLB Multiple Hit Exception....................................................................
3.6.5
Data TLB Miss Exception ...............................................................................
3.6.6
Data TLB Protection Violation Exception........................................................
3.6.7
Initial Page Write Exception............................................................................
Memory-Mapped TLB Configuration...........................................................................
3.7.1
ITLB Address Array........................................................................................
3.7.2
ITLB Data Array 1..........................................................................................
3.7.3
ITLB Data Array 2..........................................................................................
3.7.4
UTLB Address Array ......................................................................................
3.7.5
UTLB Data Array 1.........................................................................................
3.7.6
UTLB Data Array 2.........................................................................................
Instruction TLB (ITLB) Configuration.............................................................
Address Translation Method............................................................................
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3.5
3.6
3.7
Section 4
4.1
Caches
..........................................................................................................
Overview.....................................................................................................................
4.1.1
Features...........................................................................................................
4.1.2
Register Configuration.....................................................................................
Register Descriptions...................................................................................................
Operand Cache (OC)....................................................................................................
4.3.1
Configuration..................................................................................................
4.3.2
Read Operation ...............................................................................................
4.3.3
Write Operation...............................................................................................
4.3.4
Write-Back Buffer...........................................................................................
4.3.5
Write-Through Buffer......................................................................................
4.3.6
RAM Mode.....................................................................................................
4.3.7
OC Index Mode...............................................................................................
4.3.8
Coherency between Cache and External Memory.............................................
4.3.9
Prefetch Operation...........................................................................................
Instruction Cache (IC)..................................................................................................
4.4.1
Configuration..................................................................................................
4.4.2
Read Operation ............................................................................................... 102
4.4.3
IC Index Mode................................................................................................ 102
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4.2
4.3
4.4