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Rev. 3.0, 04/02, page xix of xxxviii
22.6.2 Interrupts from External PCI Devices............................................................... 921
22.6.3
,17$
.............................................................................................................. 921
Error Detection............................................................................................................ 922
PCIC Clock ................................................................................................................. 922
Power Management...................................................................................................... 923
22.9.1 Power Management Overview......................................................................... 923
22.9.2 Stopping the Clock.......................................................................................... 924
22.9.3 Compatibility with Standby and Sleep.............................................................. 927
22.10 Port Functions.............................................................................................................. 927
22.11 Version Management................................................................................................... 928
22.7
22.8
22.9
Section 23 Electrical Characteristics
.......................................................................... 929
23.1
Absolute Maximum Ratings......................................................................................... 929
23.2
DC Characteristics....................................................................................................... 930
23.3
AC Characteristics....................................................................................................... 948
23.3.1 Clock and Control Signal Timing..................................................................... 950
23.3.2 Control Signal Timing..................................................................................... 961
23.3.3 Bus Timing ..................................................................................................... 964
23.3.4 Peripheral Module Signal Timing .................................................................. 1015
23.3.5 AC Characteristic Test Conditions................................................................. 1027
23.3.6 Change in Delay Time Based on Load Capacitance........................................ 1028
Appendix A
Address List
.......................................................................................... 1031
Appendix B
Package Dimensions
........................................................................... 1039
Appendix C
Mode Pin Settings
............................................................................... 1041
Appendix D
D.1
Pin States................................................................................................................... 1044
D.2
Handling of Unused Pins............................................................................................ 1048
Pin Functions
........................................................................................ 1044
Appendix E
Synchronous DRAM Address Multiplexing Tables
................... 1050
Appendix F
Instruction Prefetching and Its Side Effects
................................... 1061
Appendix G
Power-On and Power-Off Procedures
............................................. 1062
Appendix H
List of Models
...................................................................................... 1063