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Rev. 6.0, 07/02, page 981 of 986
Index
A
Address Space...........................................64
B
Big endian.................................................53
Bus Arbitration........................................480
Bus State Controller................................311
Address Multiplexing..........................399
Areas...........................................319, 382
Burst Access........................................402
Burst ROM Interface...........................441
Byte Control SRAM Interface.............473
DRAM Interface .................................395
EDO Mode..........................................403
Endian.................................................370
I/O card interface ........................322, 444
IC memory card interface............322, 444
Master Mode.......................................483
MPX Interface.....................................455
Partial-Sharing Master Mode..............485
PCMCIA Interface..............................444
PCMCIA Support................................322
RAS Down Mode................................404
Refresh Timing ...................................409
Refreshing...........................................431
Slave Mode .........................................484
SRAM Interface..................................387
Synchronous DRAM Interface............413
Wait State Control...............................401
Waits between Access Cycles.............478
C
Caches.......................................................95
Address Array.............112, 114, 117, 119
cache fill..............................................108
Data Array...................113, 115, 118, 120
IC Index Mode....................................111
Instruction Cache ..........................95, 108
OC Index Mode...................................107
Operand Cache................................95, 99
prefetch................................................122
Prefetch Operation...............................108
RAM Mode .........................................106
Store Queues .......................................122
Tag...............................................102, 110
U bit.....................................................102
V bit.............................................102, 110
Write-Back Buffer...............................105
Write-Through Buffer .........................105
Clock Oscillation Circuits .......................247
Bus Clock Division Ratio....................258
Changing the Frequency......................257
Clock Operating Modes.......................253
PLL Circuit..........................................257
clock pulse generator...............................247
Control Registers.................................42, 49
DBR.......................................................50
Debug base register...............................50
GBR.......................................................50
Global base register...............................50
Saved general register 15 ......................50
Saved program counter..........................50
Saved status register..............................50
SGR.......................................................50
SPC........................................................50
SR..........................................................49
SSR........................................................50
Status register........................................49
VBR.......................................................50
Vector base register...............................50
D
Data Format...............................................53
Direct Memory Access Controller...........489
Address Modes....................................519
Burst Mode..........................................523
Bus Modes...........................................522
Channel Priorities................................515
Cycle Steal Mode ................................522