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ii
3.3
3.4
Bus Width of the CS0 Area................................................................................................
Switching between Master Mode and Slave Mode............................................................
62
63
Section 4
4.1
Exception Handling
........................................................................................
Overview............................................................................................................................
4.1.1
Types of Exception Handling and Priority Order.................................................
4.1.2
Exception Handling Operations............................................................................
4.1.3
Exception Vector Table........................................................................................
Resets.................................................................................................................................
4.2.1
Types of Resets.....................................................................................................
4.2.2
Power-On Reset....................................................................................................
4.2.3
Manual Reset........................................................................................................
Address Errors....................................................................................................................
4.3.1
Sources of Address Errors....................................................................................
4.3.2
Address Error Exception Handling.......................................................................
Interrupts............................................................................................................................
4.4.1
Interrupt Sources...................................................................................................
4.4.2
Interrupt Priority Levels........................................................................................
4.4.3
Interrupt Exception Handling ...............................................................................
Exceptions Triggered by Instructions................................................................................
4.5.1
Instruction-Triggered Exception Types................................................................
4.5.2
Trap Instructions...................................................................................................
4.5.3
Illegal Slot Instructions.........................................................................................
4.5.4
General Illegal Instructions...................................................................................
When Exception Sources are Not Accepted......................................................................
4.6.1
Immediately after a Delayed Branch Instruction..................................................
4.6.2
Immediately after an Interrupt-Disabled Instruction............................................
Stack Status after Exception Handling ..............................................................................
Usage Notes .......................................................................................................................
4.8.1
Value of Stack Pointer (SP)..................................................................................
4.8.2
Value of Vector Base Register (VBR)..................................................................
4.8.3
Address Errors Caused by Stacking of Address Error Exception Handling ........
4.8.4
Manual Reset during Register Access..................................................................
65
65
65
66
67
69
69
70
70
71
71
72
72
72
73
73
74
74
74
74
75
75
75
76
76
76
76
76
77
77
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Section 5
5.1
Interrupt Controller (INTC)
.........................................................................
Overview............................................................................................................................
5.1.1
Features.................................................................................................................
5.1.2
Block Diagram......................................................................................................
5.1.3
Pin Configuration..................................................................................................
5.1.4
Register Configuration..........................................................................................
Interrupt Sources................................................................................................................
5.2.1
NMI Interrupt........................................................................................................
5.2.2
User Break Interrupt .............................................................................................
79
79
79
79
81
81
82
82
82
5.2