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Rev. 2.0, 09/02, page 722 of 732
Item
Page
Revisions (See Manual for Details)
Description amended.
Bit
Bit
Name
Description
0
SDTRF
Serial Data Transfer Control Flag
Indicates whether H-UDI registers can be
accessed by the CPU. The SDTRF bit is
initialized by the
TRST
signal, but is not
initialized in software standby mode.
0: Serial transfer to SDDR has ended,
and SDDR can be accessed
1: Serial transfer to SDDR is in progress
22.3.2 Status Register
(SDSR)
603
23.5.5 AUD Start-up
Sequence
620
Add.
24.3.1 Sleep Mode
Transition to Sleep
Mode
628
Description added.
Transition to Sleep Mode:
If SLEEP instruction is executed
while the SSBY bit in SBYCR = 0, the CPU enters sleep
mode. In sleep mode, CPU operation stops, however the
contents of the CPU's internal registers are retained.
Peripheral functions except the CPU do not stop.
In sleep mode, data should not be accessed by the DMAC,
DTC, or AUD.
24.3.1 Sleep Mode
Clearing Sleep Mode
628
Description deleted.
Clearing by an interrupt
Clearing by DMAC/DTC address error
Description amended.
Clearing by the power-on reset
When the
RES
pin is driven low, the CPU enters the
reset state. When the
RES
pin is driven high after the
elapse of the specified reset input period, the CPU starts
the reset exception handling.
When an internal Power-on reset by WDT occurs, sleep
mode is also cleared.
Clearing by the manual reset
When the
MRES
pin is driven low while the
RES
pin is
high, the CPU shifts to the manual reset state and thus
sleep mode is cleared.
When an internal manual reset by WDT occurs, sleep
mode is also cleared.