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Rev. 2.0, 09/02, page 417 of 732
Table 14.2 Transfer Format
SAR
Bit 0
SARX
Bit 0
FS
FSX
Operating Mode
0
0
I
2
C bus format
Enables the slave addresses in SAR and SARX
I
0
1
2
C bus format
Enables the slave address in SAR
Disables the slave address in SARX
I
1
0
2
C bus format
Enables the slave address in SARX
Disables the slave address in SAR
Clock- synchronous serial format
1
1
Disables the slave addresses in SAR and SARX
14.3.3
Second Slave-Address Register (SARX)
SARX is an 8-bit readable/writable register that is used to set the format and store a second slave
address for the interface. When the interface is set for operation in the addressing format, the slave
address in this register has been enabled, and the upper 7 bits of the first frame to have been
transmitted after satisfaction of the start condition match the upper 7 bits of the value in SARX,
the interface has been designated, by the master device, to act as a slave device. SARX is assigned
to the same address as ICDR. Reading from and writing to SARX is only enabled when the ICE
bit in ICCR is set to 0.
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
3
2
1
SVAX6
SVAX5
SVAX4
SVAX3
SVAX2
SVAX1
SVAX0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Second slave address
A unique address, which is different from the
slave address of any other device that is
connected to the I
SVAX0 bits.
2
C bus, is set in the SVAX6 to
0
FSX
1
R/W
Format select
In conjunction with the FS bit in SAR, this bit
selects the transfer format. For the slave mode,
the FSX bit determines whether or not the slave
address in SARX is enabled. Table 14.2, in the
above description of SAR, shows the settings
selected by the values of these bits.