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Rev. 2.0, 09/02, page ix of xxxviii
Contents
Section 1 Overview........................................................................................... 1
1.1
Features.............................................................................................................................1
1.2
Internal Block Diagram.....................................................................................................3
1.3
Pin Arrangement...............................................................................................................5
1.4
Pin Functions ....................................................................................................................7
Section 2 CPU................................................................................................... 13
2.1
Features.............................................................................................................................13
2.2
Register Configuration......................................................................................................13
2.2.1
General Registers (Rn).........................................................................................13
2.2.2
Control Registers .................................................................................................15
2.2.3
System Registers..................................................................................................16
2.2.4
Initial Values of Registers....................................................................................17
2.3
Data Formats.....................................................................................................................17
2.3.1
Data Format in Registers......................................................................................17
2.3.2
Data Formats in Memory.....................................................................................17
2.3.3
Immediate Data Format .......................................................................................18
2.4
Instruction Features...........................................................................................................18
2.4.1
RISC-Type Instruction Set...................................................................................18
2.4.2
Addressing Modes ...............................................................................................22
2.4.3
Instruction Format................................................................................................25
2.5
Instruction Set...................................................................................................................28
2.5.1
Instruction Set by Classification ..........................................................................28
2.6
Processing States...............................................................................................................41
2.6.1
State Transitions...................................................................................................41
Section 3 MCU Operating Modes..................................................................... 43
3.1
Selection of Operating Modes...........................................................................................43
3.2
Input/Output Pin................................................................................................................44
3.3
Explanation of Operating Modes......................................................................................45
3.3.1
Mode 0 (MCU extension mode 0) .......................................................................45
3.3.2
Mode 1 (MCU extension mode 1) .......................................................................45
3.3.3
Mode 2 (MCU extension mode 2) .......................................................................45
3.3.4
Mode 3 (Single chip mode)..................................................................................45
3.3.5
Clock mode..........................................................................................................45
3.4
Address Map.....................................................................................................................46
3.5
Initial State in This LSI.....................................................................................................46