參數(shù)資料
型號: SED1520D0A
廠商: Electronic Theatre Controls, Inc.
英文描述: DOT MATRIX LCD DRIVER
中文描述: 點陣液晶驅動
文件頁數(shù): 12/52頁
文件大?。?/td> 204K
代理商: SED1520D0A
2.3.7 – 2.3.8
2.0 Block Diagrams
S-MOS Systems, Inc. 150 River Oaks Parkway San Jose, CA 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
371-1.0
12
2.3.7 Common Timing Generator
This circuit generates common timing and frame (FR) signals from the basic clock (CL). The Se-
lect Duty command selects a duty of 1/16 or 1/32. The 1/32 duty is achieved by a two-chip (master
and slave) configuration (common multi-chip system).
2.3.7.1
Common Timing Diagram
2.3.8 Display Data Latch Circuit
The display data latch circuit temporarily stores the data which will be output from the display
data RAM to the LCD
driver circuit at one-common intervals. The display ON/OFF and Static
Driver ON/OFF commands control the latched data so that the data in the display data RAM
remains unchanged.
0
1
2
14 15
0
1
15
16 17
30 31
16 17
31
FR
(Master
Output)
Master
Common
Slave
Common
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