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參數(shù)資料
| 型號： | SDA9380-B21 |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | EDDC Enhanced Deflection Controller and RGB Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, MQFP-64 |
| 文件頁數(shù)： | 54/72頁 |
| 文件大?。?/td> | 366K |
| 代理商： | SDA9380-B21 |
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SDA 9380 - B21
Preliminary Data Sheet
Recommended operating conditions
Micronas
8-46
2001-01-29
Maximum input current during
clamping
I
i-clamp
100
μA
Internal bias during clamping
V
clamp
V
o
0.6
V
Difference between black level of
internal and external signals at the
outputs
50
mV
Delay difference of the three
channels
t
d
0
ns
1)
Fast Blanking Input FBL1 (RGB/YUV 1)
Input voltage no data insertion
V
i-n
0.5
V
Input voltage data insertion
V
i-y
0.9
V
Maximum input voltage
V
i-max
3.3
V
Difference between transit times for
signal switching and signal insertion
t
s
- t
i
10
ns
1)
Suppression of internal video signals
(insertion) or external video signals
(no insertion)
55
dB
f
i
= 0 to 10 MHz, 1)
Fast Blanking/Contrast Reduction Input FBL2 (RGB2)
Maximum input voltage
V
i-max
3.3
V
Difference between transit times for
signal switching and signal insertion
t
s
- t
i
10
ns
1)
Suppression of internal video signals
(insertion) or external video signals
(no insertion)
55
dB
f
i
= 0 to 10 MHz, 1)
Fast Blanking
(Control bit COR1..COR0 = 00)
Input voltage no data insertion
V
i-n
0.5
V
Input voltage data insertion
V
i-y
0.9
V
Fast Blanking and Contrast Reduction
(Control bit COR1..COR0 = 01...11)
Input voltage no contrast reduction
of internal RGB signals
V
icr-n
1.4
0.5
V
FBL2L = 0
FBL2L = 1
Input voltage contrast reduction of
internal RGB signals
V
icr-y
1.7
0.9
V
FBL2L = 0
FBL2L = 1
Contrast reduction (control bit
COR1..COR0)
0
75
%
Input voltage no data insertion
V
i-n
2
1.2
V
FBL2L = 0
FBL2L = 1
Parameter
Symbol
Min
Nom
Max
Unit
Remark
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