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參數(shù)資料
| 型號(hào)： | SDA9380-B21 |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | EDDC Enhanced Deflection Controller and RGB Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, MQFP-64 |
| 文件頁(yè)數(shù)： | 40/72頁(yè) |
| 文件大?。?/td> | 366K |
| 代理商： | SDA9380-B21 |
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SDA 9380 - B21
Preliminary Data Sheet
System description
Micronas
5-32
2001-01-29
Internal v
ertical blanking pulse VBL when JMP = 0 and number of lines per field = constant
b) Description of VBL when JMP= 1
Start of VBL =
VBS
lines before the first complete line of the next field
(def. value 0)
if
BSE
= 0
end of VBL = end of line (
VBE
+ 29) (odd field)
width of VBL = (
VBS
+
VBE
+ 29) lines (odd field)(def. value 29)
if
BSE
= 1
end of VBL = end of line (
RPP
+
VBE
+ 25) (odd field)
width of VBL = (
VBS
+
RPP
+
VBE
+ 25) lines (odd field)
Note! If
JMP
= 1 the number of lines between the last ref. pulse and the end of
VBL is defined by
VBE
in the range of 7 (VBE = 0) to 14 (VBE = 7).
1 line
2 lines
VBL
(default:
BSE=0,
VBS=0,
VBE=0)
HSYNC
VSYNC
VD-
22 lines
24 lines
VBL
(BSE=0,
VBS=2,
VBE=0)
15
1
2
16
17
18
19
20
21
22
23
24
25
R G B
VBL
(BSE=1,
RPP=1,
VBS=0,
VBE =1)
20 lines
R G B
R G B
R G B
odd field
even field
odd field
even field
odd field
even field
start of even field
start of odd field
R G B
R G B
A
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