參數(shù)資料
型號: SDA9380-B21
廠商: MICRONAS SEMICONDUCTOR HOLDING AG
元件分類: 消費(fèi)家電
英文描述: EDDC Enhanced Deflection Controller and RGB Processor
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: PLASTIC, MQFP-64
文件頁數(shù): 36/72頁
文件大?。?/td> 366K
代理商: SDA9380-B21
SDA 9380 - B21
Preliminary Data Sheet
System description
Micronas
5-28
2001-01-29
The
Status byte
includes the following bits:
- HPON:
H-protection on
0: normal operation of the line output stage
1: upper threshold on input HPROT has been exceeded *)
- VPON:
V-protection on
0: normal operation of the vertical output stage
1: incorrect signal on input VPROT has been detected *)
- CON:
Coincidence not
0: H-coincidence detected
1: no H-coincidence detected
- H38K:
38 kHz line frequency
0: 38 kHz line frequency not detected
1: 38 kHz line frequency detected
- H35K:
35 kHz line frequency
0: 35 kHz line frequency not detected
1: 35 kHz line frequency detected
- CLOW:
Control loop out of window
0: all control loops inside of window
1: one of the control loop out of window
- PONRES:
Power On Reset
0: after bus master has read the status byte
1: after each detected reset
*) Also output PROTON (pin 35) goes High if HPON=1 or VPON=1.
Note!
PONRES is reset after this byte has been read.
HPON
VPON
CON
H38K
H35K
CLOW
-
PONRES
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