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參數(shù)資料
| 型號： | SDA9380-B21 |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | EDDC Enhanced Deflection Controller and RGB Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, MQFP-64 |
| 文件頁數(shù)： | 30/72頁 |
| 文件大小： | 366K |
| 代理商： | SDA9380-B21 |
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SDA 9380 - B21
Preliminary Data Sheet
System description
Micronas
5-22
2001-01-29
- NOISYVCR:Handling of noisy input signals in VCR mode
0: normal handling
1: improved handling
Note: this bit is don’t care if bit VCR = 0 (TV mode)
- HSWMI:
Minimum width of HSYNC
0: 1.5μs
1: 0.8μs
- TC_3RD:
Third time constant
0: slow VCR time constant
1: fast VCR time constant
Note: this bit is don’t care if bit VCR = 0 (TV mode)
Warnings/Notes:
1) A change of INCR causes changes of the generated clock frequency more than the
specified 4.5%.
Switching from PLL mode to Generator mode (GENMOD) with constant INCR values does not
result in exceeding the specified frequency deviation range.
2) If pin SSD has H-level the output signal HD starts immediately after power on. In this case the
starting horizontal frequency is 31.25kHz (if FH1_2 = High). Starting with other frequencies requires
L-level at SSD so that INCR can be changed before enabling HD with HDE=1.
3) When SSD = High and FH1_2 = Low the horizontal frequency is fixed to 18.75 kHz (INCR = 20)
and cannot be changed via I2C bus. Other H-frequencies in the range of 15.6 kHz to 19 kHz are pos-
sible when SSD = Low.
4) The timing of the built-in soft start circuit (starting frequency, period, ending frequency) depends
on INCR. The starting frequency of the output HD is approx. 1.71* FH, the frequency stops at FH
defined by INCR (see table on previous page) The total soft start takes about 2.66*103/FH. If the fre-
quency of the HSYNC input signal is outside the lock range of the PLL (+/- 4.5%), that means the
PLL cannot lock, the timing of the soft start may change max. +/- 4.5% due to the unlocked PLL.
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