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參數(shù)資料
| 型號(hào)： | SDA9380-B21 |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | EDDC Enhanced Deflection Controller and RGB Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, MQFP-64 |
| 文件頁(yè)數(shù)： | 28/72頁(yè) |
| 文件大?。?/td> | 366K |
| 代理商： | SDA9380-B21 |
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SDA 9380 - B21
Preliminary Data Sheet
System description
Micronas
5-20
2001-01-29
The
Vertical sync control byte
includes the following bits:
- SSC:
Sandcastle without VBL
0: output SCP with VBL component
1: output SCP without VBL component
- NI:
Non interlace
0: interlace depends on source
1: no interlace
The
PWM control byte
includes the following bits:
- PWMS1..
PWMS0: PWM select
x0: same duty cycle in each line selected (adjustable by PWMC)
01: positive V-parabola after external integration available (amplitude
adjustable by PWMC)
11: negative V-parabola after external integration available (amplitude
adjustable by PWMC)
- PWMC5..
PWMC0: PWM control
These bits control either the duty cycle or the parabola amplitude
depending on PWMS0 according to the following table (if PWMS0 = 0
also PWMS1 defines the the duty cycle):
1)
V
OH
: PWM output High level, V
OL
: PWM output Low level
The PWM output may be used as switching output when PWMS0 = 0. If PWMC = 100000
and PWMS1 = 0 the output is Low. If PWMC = 011111 the output is continously High.
X
X
SSC
X
NI
X
X
X
PWMC5
PWMC4
PWMC3
PWMC2
PWMC1
PWMC0
PWMS1
PWMS0
PWMC5...PWMC0
Duty cycle
(PWMS0 = 0)
PWMS1/108
(32+PWMS1)/108
(64+PWMS1)/108
(96+PWMS1)/108
1
Amplitude of V-parabola
(ext. integration, PWMS0 = 1)
0.46 * (V
OH
-V
OL
)
1)
0.58 * (V
OH
-V
OL
)
1)
0.69 * (V
OH
-V
OL
)
1)
0.81 * (V
OH
-V
OL
)
1)
0.91 * (V
OH
-V
OL
)
1)
100000
110000
000000
010000
011111
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