參數(shù)資料
型號(hào)： SDA9380-B21
廠(chǎng)商： MICRONAS SEMICONDUCTOR HOLDING AG
元件分類(lèi)： 消費(fèi)家電
英文描述： EDDC Enhanced Deflection Controller and RGB Processor
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： PLASTIC, MQFP-64
文件頁(yè)數(shù)： 16/72頁(yè)
文件大小： 366K
代理商： SDA9380-B21
SDA 9380 - B21
Preliminary Data Sheet
System description
Micronas
5-8
2001-01-29
within 85ms to its final value. The high time is kept constant. The normal operating pulse ratio H/L is
either 45/55 or 40/60 (selectable by I2C). A watch dog function limits an increasing of the HD period
to max. +10%.
The implemented Black Switch-Off behaviour is defined by two I
2
C bits (BSO1, BSO0). When
enabled the signal at BSOIN (e.g. the supply voltage of the line output stage) is watched. If its level
does not come up to a defined threshold Black Swich-Off is started (see 11.2). At first the RGB out-
puts are switched to continuous blanking immediately and the vertical output signals are changed to
about 115..120% overscan. After a delay of 42 lines the picture tube capacitance is discharged with
a current of some mA. From now the vertical overscan rate is calculated depending on the actual
voltage at BSOIN to get the desired deflection angle. Three relations are selectable by I
2
C. After the
voltage at BSOIN is dropped down to about 20% of its initial value the output HD and the overscan
calculation may stop.
The protection circuit watches an EHT reference and the saw-tooth of the vertical output stage. If
the EHT succeeds a defined threshold or if the V-deflection fails (refer to 11.5) the related bit is set in
the status byte and the output PROTON goes High. The output HD is deactivated (H-level) immedi-
ately independent of the selected Black Switch-Off function.
HPROT:
input
V
i
< V2
V
i
> V1
V2
≤
=
V
i
< V1
continuous blanking
HD disabled
operating range
VPROT:
vertical saw-tooth voltage
V
i
< V1 in first half of V-period
or V
i
> V2 in second half : HD disabled
The pin SCP delivers the composite blanking signal SCP. It contains burst (V
b
), H-blanking HBL
(V
HBL
) and selectable V-blanking (control bit SSC). The phase and width of the H-blanking period
can be varied by I
2
C-Bus. For the timing following settings are possible :
BD = 1
BD = 0, BSE = 0 (default value)
BD = 0, BSE = 1(alignment range)
: T
BL
= 0
: T
HBL
= t
f
(H-flyback time)
: T
HBL
= (4 * H_blanking-time + 1) / CLL
: T
DBL
= (H_shift + 4 * H_blanking_phase
- 2*H_blanking_time + 45) / CLL
: T
BL
= T
VBL
during V-blanking period
: T
BL
is always T
HBL
SSC = 0
SSC = 1
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