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參數(shù)資料
| 型號： | SDA9380-B21 |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費家電 |
| 英文描述： | EDDC Enhanced Deflection Controller and RGB Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, MQFP-64 |
| 文件頁數(shù)： | 13/72頁 |
| 文件大小： | 366K |
| 代理商： | SDA9380-B21 |
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SDA 9380 - B21
Preliminary Data Sheet
Pin configuration
Micronas
4-5
2001-01-29
4.1
Pin description
Pin No.
Name
Type
I/TTL
Q
Description
Input for external line locked clock *)
Reference oscillator output, Crystal
Reference oscillator input, Crystal
Switching between internal (L) and external clock (H) *)
Switching between normal operation (TEST=L) and test mode
(TEST=H: pins 4, 12, 13, 14, 15, 17, 49, 50, 63, 64 are additio-
nal test pins)
Substrate pin, has to be connected to ground whenever a
power supply or signal is applied
Reset input, active Low
I2C Bus clock
I2C Bus data
Digital supply
Digital ground
Control signal output for H driver stage (open drain)
Goes High when frequency of HSYNC is about 35kHz or more
Goes High when frequency of HSYNC is about 38kHz
Pulse width modulated control signal output
V-sync input
Switching between 1f
H
mode (L) and 2f
H
mode (H)
HSYNC input (CLEXT=H: TTL; CLEXT=L: analog) *)
Analog supply
Analog ground
Line flyback for H-delay compensation
Analog supply
Analog ground
Control signal output for East-West raster correction
Output of an I2C Bus controlled DC voltage
Control signal output for DC coupled V-output stage
Like VD+
Analog supply
Analog ground
Watching external V-output stage (input is the V-saw-tooth from
feedback resistor)
Watching EHT (input is e.g. H-flyback)
Watching B+ when frequency of HD has to be decreased
Input for starting Black Switch-Off
Input for a beam current dependent signal for stabilization of
width, height and H-phase
Protection on (goes High after response of H- or V-protection)
1
2
3
4
5
CLKI
X2
X1
CLEXT
TEST
I
I/TTL
I/TTL
6
SUBST
S
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
RESN
SCL
SDA
VDD(D)
VSS(D)
HD
H35K
H38K
PWM
VSYNC
FH1_2
HSYNC
VDD(A1)
VSS(A1)
Φ
2
VDD(A2)
VSS(A2)
E/W
D/A
VD+
VD-
VDD(A3)
VSS(A3)
VPROT
I/TTL
I
IQ
S
S
Q
Q/TTL
Q/TTL
Q/TTL
I/TTL
I/TTL
I
S
S
I
S
S
Q
Q
Q
Q
S
S
I
31
32
33
34
HPROT
HSAFE
BSOIN
IBEAM
I
I
I
I
35
PROTON
Q/TTL
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