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參數(shù)資料
| 型號(hào)： | SDA9254-2 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter |
| 中文描述： | VIDEO DRAM, PQFP64 |
| 封裝： | PLASTIC, MQFP-64 |
| 文件頁數(shù)： | 1/32頁 |
| 文件大?。?/td> | 183K |
| 代理商： | SDA9254-2 |
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Type
Ordering Code
Package
SDA 9254-2
on request
P-MQFP-64-1
2.6 MBit Dynamic Sequential Access Memory
for Television Applications (TV-SAM) with
On-chip Noise Reduction Filter
Preliminary Data
CMOS IC
SDA 9254-2
P-MQFP-64-1
Features
G
Stores a complete video field (4:1:1)
G
On chip adaptive recursive noise reduction filter (4:1:1)
G
4 noise reduction classes selectable
G
Special noise reduction mode for 4:2:2 applications
G
212
×
64
×
16
×
12-bit organization
G
Triple port architecture
G
One 16
×
12-bit input shift register
G
Two 16
×
12-bit output shift registers
G
Shift registers independently and simultaneously
accessible (one output shift register is used internally for
noise reduction filtering)
G
Continuous data flow even at maximum speed
G
40-MHz shift rate - 0.96-Gbit/s total data rate
G
All inputs and outputs TTL-compatible
G
Tristate outputs
G
Random access of groups of 16
×
12 bits for a wide range
of applications
G
Refresh-free operation possible
G
5 V
±
10 % power supply
G
0 … 70
°
C operating temperature range
G
Low power dissipation: 700 mW active, 28 mW standby
G
Suitable for all common TV standards
G
Allows flicker and noise reduction simultaneously
with only one field memory
G
Applications: TV, VCR, image processing,
video printers, data compressors, delay lines,
time base correctors, HDTV
Semiconductor Group
1
1998-01-16
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