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參數(shù)資料
| 型號(hào)： | SDA5252-2 |
| 廠商： | SIEMENS A G |
| 元件分類： | 圖文 |
| 英文描述： | ICs for Consumer Electronics |
| 中文描述： | TELETEXT DECODER, PDIP52 |
| 文件頁數(shù)： | 21/23頁 |
| 文件大?。?/td> | 147K |
| 代理商： | SDA5252-2 |
SDA 525X-2
Semiconductor Group
21
1998-10-08
E800- F3FF: reserved for future extensions (3k)
F400 - F7FF: VBI buffer (1k)
F800 - FBFF: CPU RAM (1k)
FC00- FFFF: reserved for future extensions (1k)
8
All calls of the subroutine “adjust_horizontal” (inside the module IFRDEMO.C51 on the
Firmware Demo Disk) must be removed from the external controller software. This
routine was developed to adjust the display to the middle of the screen according to
tolerances of the LC-oscillator. This oscillator is not used any more. The pixel clock is
derived from the single external crystal. However, customers who are using SDA 525x-2
without emulating with SDA 5250-2 or 5250M-2 need to use some adjustment routine for
their first circuits. As soon as the correct adjustment is known, it can be used as a fixed
value for initialization or for future software.
Furthermore, due to some changes in the special function registers, the software needs
to be checked. The changes are in detail:
1. The serial interface is not supported any longer. By this, registers SCON and SBUF
are no longer available. The “Serial Interrupt Enable Flag” ES of the Interrupt Enable
register (Bit 4 of A8) must not be written (default after reset = 0).
2. The functions and bits Prescaler Control (PSC) and ADC sample time (STADC) of the
Special Function Register ADCON are not available any more. Bits 7 and 6 of D8 must
be 0.
3. The registers following must not be written. The software needs to be checked
accordingly.
SBUF (99):
Bits 0 to 7
SCON (98):
Bits 0 to 7
ACQMS2 (C2):
Bits 0 to 7
DMODE2 (C7):
Bits 5 to 7
ADCON (D8):
Bits 6 and 7
IE (A8):
Bit 4
The allowed bits of DMODE2, ADCON and IE have to be changed with the commands
ANL or ORL.
Software Changes
9
Although the frequency of the external quarz is now 6 MHz, all the internal timings
correspond to that of the SDA525x with an 18 MHz quarz. This is achieved by an internal
PLL.
Timing
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